A low-power rail-to-rail operational amplifier with enhanced linearity is designed and implemented to address the signal distortion problem of the Class-AB output stage of operational amplifiers. Based on a mechanism analysis of the non-ideal higher-order effect caused by the short channel, a linearly enhanced floating current source structure is proposed, which effectively reduces the circuit gain nonlinearity and decreases the distortion problem during signal processing while controlling the power consumption through the application of the translinear loop. A circuit prototype is fabricated using a 0.18-m process, and the test results show that the chip realizes a rail-to-rail input-output range with a gain nonlinearity of 5.5×10−6, a quiescent current of 39 A, and an open-loop gain of 119.5 dB.

This article proposes a current mode control BUCK structure with a fast response and high efficiency by designing a high-speed output detection circuit. When switching between loads, the system loop quickly responds, and the transient bias current rapidly increases, resulting in a smaller transient voltage. The proposed instantaneous gain enhancement path structure is implemented with a TSMC 180-nm process. Simulation results show that in typical applications, when the load current switches between 1 and 1.5 A, the transient output voltage is within 26 mV. The transient voltages of traditional structures with and without feedforward capacitors are 46 and 74 mV, respectively; thus, the proposed system reduces these by approximately 43% and 65%, respectively, and significantly improves transient response speeds. Additionally, the peak efficiency can reach 96%.

A low temperature bleach bandgap reference source with segmental curvature compensation is designed to solve the problem of poor first-order bandgap reference temperature coefficient. The conventional first-order bandgap reference is compensated by segmental curvature, and two types of exponential compensation currents varying with temperature are generated using a MOS tube operating in the subthreshold region. The first-order coefficient temperature curve is compensated at both high and low temperatures, and the temperature coefficient of the bandgap reference source is reduced. The results of a SMIC 0.18 m CMOS process simulation show that the bandgap reference output voltage is 1.075 V at a supply voltage of 3.3 V. The bandgap reference designed in this paper is compared with a first-order bandgap reference without curvature compensation. The temperature coefficient decreases from 9.85×10−6/℃ to 1.58×10−6/℃ in the temperature range of −40–125 ℃ at the TT corner, and the power supply rejection ratio is −46.4 dB at 100 Hz.

A high linearity broadband IQ modulator circuit designed in a 0.1 m GaAs PHEMT process is presented. It can support a baseband bandwidth of 0–2.5 GHz and RF bandwidth of 3–20 GHz. A three-stage cascaded passive polyphase filter (PPF) is used to generate four phase quadrature broadband signals in the local oscillator chain. Shunt peaking is adopted to expand the bandwidth of the RF driver amplifier and an active Gilbert mixer is designed to acquire a certain gain. The linearity of the modulator is improved by optimizing the amplitude of the local oscillator driving signal, and the modulator chip is applied to high performance measuring equipment. Circuit simulation results show that the output frequency covers 3–20 GHz, the in-band conversion gain is greater than 7.5 dB, OIP3 is greater than 21.8 dBm, OP1dB is greater than 12.7 dB, and the input/output return loss performance is excellent. The circuit measurement results show that the in-band conversion gain is no less than 5.7 dB, OIP3 is no less than 20.26 dBm, and the total power consumption of the chip is 3.4 W.

To avoid selecting an excessively large tuning gain Kvco causing degradation in the phase noise of phase-locked loop frequency synthesizers and various adverse effects from non-optimal sub-band selection, we propose a precise automatic frequency calibration (AFC) algorithm to achieve the accurate selection of voltage-controlled oscillator (VCO) frequency sub-bands. Furthermore, to further improve its noise performance, we propose a method for optimizing noise by adjusting the oscillation amplitude of a voltage-biased VCO, while avoiding excessive power consumption. A phase-locked loop frequency synthesizer is fabricated using SMIC 0.11 m CMOS technology, with a VCO operating frequency range of 1.7–2.6 GHz. After division by four, the phase noise at a frequency deviation of 1 MHz from a local oscillator frequency of 433.92 MHz is −129.59 dBc/Hz. The total power consumption of the proposed frequency synthesizer is 4.8 mW, with an area of 0.32 mm2.

A comparator delay-compensated relaxation oscillator was designed by clamping the peak voltage during the capacitor charging phase to a set reference voltage to mitigate the effects of comparator delay. The circuit and layout were implemented using the SMIC 0.18 m process. Post-simulation results showed an oscillator output frequency of 640 kHz, with a temperature variation rate of ±0.27% across a temperature range of −40 to 125 °C and power supply sensitivity of ±0.48%/V within a voltage range of 2.5–3.3 V.

This paper introduces a voltage-controlled oscillator (VCO) with low phase noise and low power consumption, implemented using a 65-nm CMOS technology. The design features a resonator with dual cross-coupled PMOS transistors and an AC-coupled variable capacitor, reducing VCO gain and significantly improving phase noise. Moreover, the design incorporates six sets of switchable capacitors to broaden the tuning range of the oscillator, resulting in a wide frequency spectrum while preserving low phase noise. Post-simulation results show that at a supply voltage of 1.2 V, the VCO consumes 3.49 mW and has an oscillation frequency range from 4.78 to 5.24 GHz. At an output frequency of 4.90 GHz, the phase noise measures −128.66 dBc/Hz at a 1 MHz offset, and the root mean square jitter is 425.85 fs. This low-noise, low-power, wide-bandwidth VCO is ideal for high-precision clocks, wireless systems, and high-speed data converters requiring quality clock signals.

A wake-up receiver with an ultra-low-power envelope detector (ED) front structure is designed to address the sensitivity-power compromise problem of wireless receivers. Based on the analysis of the sensitivity constraint mechanism of this wake-up receiver, a passive differential envelope detector with a high input impedance is introduced to replace the traditional active envelope detector, and its design is optimized to reduce the power consumption of the system and improve the conversion gain and reception sensitivity. Designed using the 65-nm CMOS process, simulation results show that, driven by a 0.4 V supply voltage, on–off keying (OOK) signal with carrier frequency of 434 MHz, and data rate of 200 bits/s, the wake-up receiver consumes 16 nW and has a sensitivity of −68 dBm, which, compared with other devices, achieves a 44.7% sensitivity improvement with comparable power consumption. The 44.7% improvement in the sensitivity with the figure-of-merit (FoM) value is comparable to a 43.3% reduction in power consumption.

A low-noise low-dropout (LDO) circuit with base current compensation is designed in a 180-nm bipolar–CMOS–DMOS (BCD) process. A bipolar junction transistor (BJT) pre-amplifier stage is used in the LDO to reduce the 1/f noise of the error amplifier. A unity-gain negative feedback architecture is utilized to eliminate the noise generated by the feedback resistor network, and a first-order RC low-pass filter is used to attenuate the high-frequency noise of the reference. Additionally, a base current compensation circuit is proposed to compensate for the base current of the BJT pre-amplifier stage, thereby preventing the decrease in the reference voltage. Simulation result shows that the LDO has an input voltage of 2.4–5.5 V, output voltage of 0.8–5.3 V, and maximum load current of 500 mA. The output noise spectral density at 1 kHz is 4 nV/{L-End}Hz, and the integrated noise from 10 Hz to 100 kHz is 0.92 VRMS.

In this study, a high-precision capacitive sensing chip is designed using a 180-nm 1.8-V CMOS process. The chip employs a discrete-time second-order chain of integrators with weighted feed-forward summation (CIFF) structure Sigma-Delta modulator as the front-end circuit for capacitive detection. Techniques such as chopper-stabilized differential amplifiers, gate-bootstrapped switches, and lower plate sampling are utilized to enhance the accuracy of capacitance measurement. The overall circuit is simulated using software, and the results indicate that the capacitive sensing circuit can accurately detect capacitances ranging from 0 to 32 pF. At a measurement frequency of 10 Hz, the chip achieves an absolute capacitance resolution of approximately 10 aF. The core circuitry of the capacitive sensing chip is fabricated, and appropriate testing environments are established to conduct post-fabrication testing and validation. The testing setup employed instruments such as oscilloscopes, and the results demonstrate that the chip has a capacitance detection range of 0 to 32 pF. At a conversion frequency of 100 Hz, the absolute capacitance resolution is approximately 1 fF, whereas at a conversion frequency of approximately 6 Hz, the absolute capacitance resolution can reach 35 aF.

A high performance receiver is designed in HL55nm CMOS technology for the 5.8 GHz Doppler Radar Applications. The receiver is mainly composed of a transconductance low-noise amplifier (LNTA), a mixer, a local oscillation (LO) buffer, and a transimpedance amplifier (TIA). The receiver utilizes a transformer to convert a single-ended signal to a differential signal for excellent common mode noise suppression. LNTA employs noise cancellation to achieve low noise, while also featuring low power consumption, no inductance, and high output impedance. The receiver is put to sleep mode by using the duty cycle to achieve extremely low power consumption at the system level. The simulation results show that, the receiver achieves 41 dB gain and 27 dB noise figure at 50 Hz without LO leakage. The IP1dB of the receiver is −28 dBm. The proposed receiver has 4.75 mW and 23.76 W power consumption in the normal mode and low power mode respectively. The test results show that the lowest NF of the receiver at 1 MHz is 26.7 dB, the highest gain is 41.6 dB, and the layout area is only 680 m×384 m.

The DC/DC converter provides stable power voltage and current for systems such as computer, communication, and telemetry and remote control systems. The power management chip is the core control unit of the power system. The radiation effect induced by various types of electromagnetic radiation in space imposes challenges to the performance indicators, reliability, and service life of electronic equipment. With the increasing development of deep space exploration and commercial aerospace systems, the demand for a high performance of power chip resistance is increasing. The pulse width modulation (PWM) controller proposed in this article is based on dual-crystal self-aimed at silicon-on-insulator (SOI) complementary bipolar techniques and adopts a various anti-radiation designs to achieve a good radical resistance. Specifically, the anti-total dosage ability of the chip is greater than 1 000 Gy (Si), and the ability to inject neutrons is greater than 2×1013 n/cm2. The chip has been applied to multiple projects, thus playing an important role in improving the anti-radiation capacity of power systems.

Based on the architecture of a gigahertz continuous-detection logarithmic amplifier and the current-feedback fast-response technology, an ultra-wideband and fast-response logarithmic amplifier is designed, while the overall architecture and operating principle of the logarithmic amplifier are introduced. The circuit comprises a limiting amplifier, a rectifier, a bias circuit, an output stage, an offset compensation structure, and other units. The principle of ultra-wideband and fast-response design technology is analyzed, whereas the circuit design, layout design, and post-simulation are completed. The results of a chip flow test show that the logarithmic amplifier operates within 0.1–2.5 GHz at an operating voltage of 5 V. Under the ±3 dB requirement for logarithmic accuracy, the dynamic range can reach 70 dB, while the response time is ≤ 100 ns.

To improve upon traditional active inductors based on current-reuse structures, a novel active inductor with low power consumption, low noise, and independently tunable inductance (L) and quality factor (Q) is proposed. The design primarily consists of a gain-enhanced common-source (CS) –common-gate (CG) composite negative transconductor (NT) with a voltage tuning terminal, a CG positive transconductor (PT), a noise suppression branch, and an active feedback amplifier. The NT and PT are connected in a current-reuse configuration, which enables inductive behavior while reducing power consumption and improving the Q factor. To further suppress noise, a noise suppression branch is introduced at the gate of the CG PT. Additionally, an active feedback amplifier with a voltage tuning terminal is added to the feedback path between the PT and NT to enhance the Q factor and compensate for variations in the Q peak caused by L tuning. This topology allows for independent tuning of the inductance value relative to the Q factor at a fixed frequency, while maintaining a nearly constant Q peak across different frequencies. The circuit also exhibits low power consumption and low noise. Fabricated using a 0.18-m CMOS process, the inductance can be tuned from 258–469 nH, representing a tuning range of 83.7%, with only a 1.4% variation in Q at a high frequency of 2.75 GHz. At operating frequencies of 2.1, 2.5, and 3.2 GHz, the Q peak values are 327, 329, and 328, respectively, showing a variation of just 0.3%. The noise is 2.99 at 1 GHz and 1.74 at 2.75 GHz. The total power consumption is only 0.96 mW.

With the increasing integration density of integrated circuits, the effect of mechanical stress accumulated during manufacturing and packaging on the electrical properties of the devices is significantly enhanced. Therefore, the detection of stress is particularly important to improve and optimize the process. In this paper, the theory and development of packaging stress measurement using silicon piezoresistive effect are introduced. The feasibility of measuring wafer stress by PCM using piezoresistive effect in chip fabrication stage is discussed, and the preliminary experimental results are obtained. The results showed that the n-type piezoresistive sensitivity of the ten-element unipolar rosette is higher than that of the eight-element bipolar rosette. When used for stress testing, the error of the ten-element unipolar rosette may be greater. Subsequent research can be carried out on the evaluation method of stress test accuracy.

As the design complexity of field programmable gate arrays (FPGAs) increases, the high density of internal units and limited routing resources can result in routing congestion. Predicting the routing congestion in the early stage of physical design and implementing strategies can effectively reduce design time and costs. This paper proposes a model for predicting FPGA routing congestion using complex networks and patched EDM (Elucidating the Design Space of Diffusion-Based Generative Model), leveraging the circuit topology characteristics preserved by complex network features. During the placement stage, circuit features and complex network features related to routing congestion are extracted and mapped into RGB images based on feature importance. Subsequently, Patch transformation is introduced to capture key congestion-related information. Experimental results show that the method achieves an average SSIM of 85.01%, PSNR of 27.854 7 dB, NRMS of 12.91%, PIX and of 18.73%, outperforming the recent state-of-the-art models.

To address the application requirements of quasi-cyclic low-density parity-check (QC-LDPC) codes in 5G new radio (NR) systems, we propose an encoding optimization method based on cyclic reconstruction of generator submatrices. This method determines the base matrix, lifting factor (Z), and generator submatrix (P) according to the code length and code rate of the input information sequence. By storing and reconstructing the generator submatrix at intervals of Z, the method effectively reduces memory resource consumption. The encoder is implemented and verified on a field programmable gate array (FPGA) platform using Verilog HDL. The results show that the optimized design reduces look-up table (LUT) resource consumption by 14.6% and register resource consumption by 54.6% compared with direct encoding, and the maximum encoding throughput can reach 2.7 Gb/s at a clock frequency of 100 MHz, which can satisfy the application requirements of high-speed coding.

The aim is to address the problems of severe congestion and difficult timing convergence in integrated circuits of deep sub-micron processes. An optimized clock tree synthesis (CTS) method integrating useful skew and layout optimization is proposed. During the layout, early clock flow is used to construct the clock tree in advance. The data flow between registers and macro-cells is analyzed for timing violations. Subsequently, scripts are employed to optimize their physical positions. Additionally, the clock tree length is adjusted with a useful skew. The method was compared with two other methods in Innovus and verified using PrimeTime. Congestion improved. The worst negative slack (WNS), total negative slack (TNS) of the setup time, and number of violated paths in the CTS stage decreased significantly. For modules of the two processes, WNS decreased by over 90% and TNS by over 96%. This indicates that the proposed method can effectively ease congestion and optimize timing.

To effectively reduce the influence of edge field effect on the micro-electromechanical systems (MEMS) microwave power detection chip of a cantilever-beam structure and improve the microwave characteristics of the detection chip, we established a cantilever-beam capacitance model in this study. The cantilever-beam structure was optimized, and the compensation effect of the array hole size and density on edge field capacitance was studied using finite element simulation software. The finite element simulation results showed that the structure was optimal when the hole size was 10 m×10 m and hole spacing was 10 m. The calculated coupling capacitance values of three MEMS cantilever beams were 67.6, 101.4, and 135.3 fF, respectively. The equivalent capacitance values obtained using the finite element simulation were 67.3, 100.5, and 134.1 fF, respectively, and the influence of the edge field capacitance of the MEMS cantilever beams decreased to 0.4%, 0.9% and 0.9%, respectively. The experimental results showed that the return loss of the detection chip was less than −10.6 dB at 8–12 GHz, and the sensitivities of the three systems at 10 GHz were 16.3, 65.6, and 144.4 fF/W, respectively, which provide reference values for studying the MEMS cantilever-beam capacitance model.

In this paper, a geometrically scalable compact model for bipolar junction transistors, derived from the standard Mextram model, is proposed. According to the physical structure and critical dimensions of an NPN transistor, such as the length and width of its emitter, the initial model parameters are modified by introducing several dimension-related factors. The revised model is verified across various process technology nodes and platforms. The results demonstrate that our model has a remarkable scaling capability, and the RMS values are significantly lower than those of a MULT-scaling model. Therefore, our scalable compact model has a promising application in SPECTRE simulation of bipolar transistors in integrated circuits.

Three-dimensional electron gas is the key to the excellent performance of polarization-doped field-effect transistors (PolFETs), but no quantitative theoretical work has been conducted on it. In this article, a quantitative theory of the three-dimensional electron gas is presented. Based on a quantitative study on the polarization effect of the AlGaN layer of graded Al components in a PolFET, the volume polarization charge distribution is calculated, and the depletion and neutral approximations of the AlGaN layer are proposed in combination with the space charge analysis. The Fermi-Dirac statistics and energy band-potential relationship are introduced to establish equations for solving the depletion width. The boundary conditions and approximation are defined, and the numerical and analytical solutions of the equation are given (the maximum relative error is less than 3%).

Gate oxide interface traps are the primary cause of reliability degradation in SiC MOSFETs. In this study, based on the structure of N-type 4H-SiC MOSFETs, the impact of gate oxide interface traps on the electrical characteristics and reliability of the devices under bias temperature stress was systematically investigated. The research results indicated that the density and energy levels of acceptor traps significantly affected the electrical characteristics, specifically manifested as a positive shift in the threshold voltage, an increase in the on-resistance, and changes in the C-V characteristic curves. The influence of donor traps on the electrical characteristics was relatively minor, primarily reflected in the capacitance changes in the accumulation region of the C-V curves. At high temperatures, the carrier capture capability of shallow-level acceptor traps significantly weakened; however, deep-level acceptor traps maintained a strong capture capability. Additionally, the hot carrier injection effect was related to the magnitude and duration of the gate stress. Increasing the gate bias and stress time led to an increase in the interface trap density and their range expands, affecting the electrical characteristics of the device and significantly degrading long-term reliability.

Low-dielectric-constant (Low-K) materials are widely utilized in chip fabrication owing to their ability to enhance overall device performance by reducing the parasitic capacitance and signal delay. However, the porous and mechanically fragile nature of Low-K materials often results in edge chipping, micro-cracking, and delamination during wafer dicing processes. This study systematically investigated the influence of various laser grooving parameters on edge quality and groove geometry in Low-K chip dicing. Subsequently, the chips obtained under different laser grooving parameters are packaged and tested for reliability. Key findings demonstrate that laser grooving parameters significantly affect dicing morphology and result in different stresses in the reliability test after packaging, thus affecting the reliability of the circuit.

With the continuous enhancement of DC/DC converter power, there has been a notable increase in heat generation, highlighting the growing significance of thermal design in ensuring product reliability. This paper addresses the issue of elevated temperatures in magnetic components within high-power hybrid integrated DC/DC converters by analyzing their heating mechanisms and heat dissipation pathways. Utilizing the finite element simulation software ANSYS Icepak, various heat dissipation schemes were modeled and analyzed. A comprehensive optimization strategy was proposed, involving filling the magnetic device with high thermal conductivity potting compound to minimize the thermal resistance between the copper winding and the magnetic core, as well as adding adhesive between the sidewalls of the magnetic core and the shell to augment the heat dissipation area. Both simulation results and physical testing have confirmed that the optimized magnetic device experiences a temperature reduction of 15.5 ℃, and the process adaptability has been validated through reliability testing.

Tin bead spatter is a common defect in the vacuum reflow process. By analyzing its causes, two main factors contributing to tin bead spatter have been identified: the quality of the component's coating and the minimum vacuum level. By pretreating the components to allow impurities in the coating to fully escape, using step-by-step vacuum pumping, dynamically adjusting the minimum vacuum level, or reducing the vacuum rate to slowly remove bubbles from the molten solder, the incidence of tin bead spatter can be effectively reduced.