The aim is to address the problems of severe congestion and difficult timing convergence in integrated circuits of deep sub-micron processes. An optimized clock tree synthesis (CTS) method integrating useful skew and layout optimization is proposed. During the layout, early clock flow is used to construct the clock tree in advance. The data flow between registers and macro-cells is analyzed for timing violations. Subsequently, scripts are employed to optimize their physical positions. Additionally, the clock tree length is adjusted with a useful skew. The method was compared with two other methods in Innovus and verified using PrimeTime. Congestion improved. The worst negative slack (WNS), total negative slack (TNS) of the setup time, and number of violated paths in the CTS stage decreased significantly. For modules of the two processes, WNS decreased by over 90% and TNS by over 96%. This indicates that the proposed method can effectively ease congestion and optimize timing.