As the design complexity of field programmable gate arrays (FPGAs) increases, the high density of internal units and limited routing resources can result in routing congestion. Predicting the routing congestion in the early stage of physical design and implementing strategies can effectively reduce design time and costs. This paper proposes a model for predicting FPGA routing congestion using complex networks and patched EDM (Elucidating the Design Space of Diffusion-Based Generative Model), leveraging the circuit topology characteristics preserved by complex network features. During the placement stage, circuit features and complex network features related to routing congestion are extracted and mapped into RGB images based on feature importance. Subsequently, Patch transformation is introduced to capture key congestion-related information. Experimental results show that the method achieves an average SSIM of 85.01%, PSNR of 27.854 7 dB, NRMS of 12.91%, PIX and of 18.73%, outperforming the recent state-of-the-art models.