With the increasing integration density of integrated circuits, the effect of mechanical stress accumulated during manufacturing and packaging on the electrical properties of the devices is significantly enhanced. Therefore, the detection of stress is particularly important to improve and optimize the process. In this paper, the theory and development of packaging stress measurement using silicon piezoresistive effect are introduced. The feasibility of measuring wafer stress by PCM using piezoresistive effect in chip fabrication stage is discussed, and the preliminary experimental results are obtained. The results showed that the n-type piezoresistive sensitivity of the ten-element unipolar rosette is higher than that of the eight-element bipolar rosette. When used for stress testing, the error of the ten-element unipolar rosette may be greater. Subsequent research can be carried out on the evaluation method of stress test accuracy.