A highly reconfigurable inductor–capacitor bandpass filter (LC BPF) is built by combining a novel voltage-controlled active inductor (VCAI) with a switched capacitor. The LC BPF primarily consists of five components: the VCAI, switched capacitors, a negative resistance generation circuit, a differential input stage, and a differential output stage. The VCAI comprises a composite structure positive transconductor with one external voltage control terminal, an enhanced negative transconductor, and a regulation circuit with two external voltage control terminals. This design allows the VCAI to achieve a wide range of adjustable inductance while maintaining a high quality factor (QL) during inductance tuning. By replacing passive spiral inductors with the VCAI and integrating it closely with other components, the LC BPF achieves high reconfigurability for continuously tuning the center frequency over a wide range and realizing a high and tunable quality factor (QF) at various center frequencies. Verification results show that the center frequency of the LC BPF can be tuned from 2.05–7.2 GHz, offering a tuning range of up to 111.3%. At center frequencies of 3.5, 5.1, and 7.2 GHz, the QF can be tuned from 6 to 71.4; the maximum 1 dB compression point is −7 dBm, the minimum noise figure is 18.5 dB, and the highest figure of merit achieved is 91.5 dB.

This study proposes a novel ultra-wideband active balun. Building on the traditional differential-pair active balun, an additional coupled differential pair is introduced to jointly compensate for gain and phase errors with their intrinsic differential-pair path. A small-signal mathematical model is analyzed and derived to verify if the proposed technique can effectively enhance the balun balance, thereby reducing both gain and phase errors. The proposed active balun is implemented using a 0.13-m CMOS process. Measurement results show that the phase and gain errors are less than 5° and 0.7 dB, respectively, across the 10–40 GHz frequency range. Owing to its simple circuit structure, the proposed balun occupies a compact area of 650 m×480 m.

This paper presents a low-power dynamic amplifier designed for a noise-shaping pipeline successive approximation register analog-to-digital converter (NS Pipe-SAR ADC). The proposed amplifier is employed in both the error feedback operational transconductance amplifier (OTA) and the inter-stage residue amplifier within the ADC system. Unlike conventional dynamic amplifiers, the proposed design is based on the floating-input amplifier (FIA) architecture and incorporates a novel body-effect-assisted level-shifting technique. Compared to traditional FIAs, the proposed amplifier requires only an additional shifting capacitor to achieve a 4-dB gain improvement at the same power consumption. Fabricated using the TSMC 65-nm CMOS process, simulation results show that the dynamic amplifier achieves the required 16× gain for the ADC system, with a bandwidth of 500 MHz and a power consumption of 50.4 W.

To address the issue of excessive power consumption caused by operational amplifier clamping in traditional bandgap reference circuits, a low-power, low-temperature-drift, non-operational amplifier bandgap reference circuit is designed based on the traditional Brokaw structure. The design is implemented using the SMIC 0.18-m CMOS process. To reduce the temperature drift of the output voltage, a curvature correction circuit is introduced. This circuit extracts both positive and negative temperature coefficient currents from a first-order bandgap reference, effectively reducing temperature-induced variations and achieving a lower temperature coefficient across a wide temperature range. Simulation results show that over the temperature range of −40 °C to 130 °C, the bandgap reference output voltage is 1.214 V, with a temperature coefficient of 2.76 × 10-6/°C. The power supply rejection ratio is −69 dB at DC, and the static current consumption of the bandgap reference is 4.7 A under a 3.3 V supply. The curvature correction circuit adds only 0.05 A of static current while reducing the temperature coefficient by 64.93%.

The design of a quadrature demodulator operating in the 0.03–2 GHz frequency range is proposed based on the SiGe process. To achieve higher linearity and improved reverse isolation, the design employs a common-base structure with negative emitter feedback and external chip inductors. The test results show that, the voltage conversion gain is greater than 4 dB, the input 1 dB compression point (IP1dB) isup to 12.1 dBm, and the third-order input intercept point (IIP3) is 27 dBm. The measured LO-to-IF leakage is less than −47 dBc, and the noise figure (NF) is below 17.3 dB. The amplitude and phase imbalances are approximately 0.04 dB and 0.7°, respectively. The demodulator maintains excellent demodulation accuracy across a wide range of LO power levels, making it well-suited for use in radio transceivers and communication systems.

This paper presents a low-phase-noise, low-power charge pump phase-locked loop (CPPLL) frequency synthesizer based on the 65-nm CMOS process. To improve phase noise performance, a symmetric PMOS cross-coupled topology is employed in the voltage-controlled oscillator (VCO). To mitigate spurious noise, a four-step adjustable reset delay chain is proposed for the phase frequency detector (PFD), combined with a low-mismatch charge pump design to reduce in-band phase noise caused by phase detection dead zones. A swallow counter divider is adopted to significantly reduce power consumption associated with high-frequency clock division. The proposed PLL operates over a frequency range of 4.80–5.38 GHz. Post-simulation results at 5 GHz show that the phase noise of the VCO and PLL at a 1 MHz offset frequency are −115 dBc/Hz and −110 dBc/Hz, respectively. The overall PLL consumes only 6.6 mW of power and occupies an area of 0.66 mm×0.64 mm. By employing a CML high-speed divide-by-two circuit, the proposed CPPLL can generate high-quality local oscillator clocks ranging from 2.40–5.38 GHz for WLAN/Wi-Fi transceivers.

True random number generators (TRNGs) play an essential role in cryptography, statistics, information technology, and other domains. Traditional TRNGs based on ring oscillators (ROs) often require extended time periods to accumulate sufficient jitter such that the post-XOR output signal falls within the jitter-dominant region. This study proposes a novel TRNG method implemented on a field-programmable gate array (FPGA), which uses RO-generated jitter as the entropy source. Unlike conventional approaches that sample RO output directly, this method extracts the phase difference between two ROs using an XOR gate chain and converts it into a pulse signal. The pulse signal is precisely counted, benefiting from the short-pulse suppression effect of logic gates, thereby enhancing sampling precision. Additionally, the output is processed through an XOR operation to reduce output bias and improve randomness. The proposed TRNG design is implemented on Xilinx Virtex-7 and Artix-7 FPGAs. The generated random sequences successfully pass both the NIST SP800-22 and NIST SP800-90B statistical tests. Furthermore, the TRNG is evaluated under various voltage and temperature conditions, demonstrating strong robustness.

A low dropout regulator (LDO) with ampere level current output, ultra-low dropout and reverse current protection has been designed. This work designed a charge pump boost circuit for internal boosting, and an anti-backflow design was added, which could conduct the current to the ground through the feedback resistors, improving the circuit safety effectively. This design is based on 0.15 m BCD process for chip verification. And the results show that the output current can reach 1 A or above, the dropout is 115 mV@1 A, and the reverse current could be less than 6 A.

Based on the SMIC 130-nm process, this study designs a bandgap reference (BGR) with high-order nonlinear curvature compensation and a low temperature coefficient. By employing curvature compensation and segmented temperature compensation techniques, the proposed BGR achieves a significantly reduced temperature coefficient and an extended operating temperature range. Operating with a 3.5 V power supply, the BGR provides a reference output voltage of approximately 1.2 V. The compensation current is adaptively adjusted based on the temperature range. Simulation results show that six extreme temperature compensation points are achieved across the range of −75 oC to 125 oC. The temperature coefficient before compensation is 11.6×10-6, which reduces to 1.137×10-6 after compensation. The BGR exhibits a power supply rejection ratio of −46.47 dB and consumes 1.78 mW of static power at low frequencies.

A sub-threshold reference voltage source with an all-CMOS structure is designed, which leverages the gate-source voltage difference of NMOS transistors with two different threshold voltages. This design eliminates the need for additional resistors and reduces the static power consumption. An output voltage generation circuit is designed that combines a unit-gain buffer based on a bipolar operational amplifier with a gate-coupled NMOS pair to realize the summation of voltages with positive and negative temperature coefficients. The layout of the reference voltage source is implemented using the TSMC 0.18-m process and occupies an area of 43 m × 14 m. Post-simulation results show that the average output voltage is 345 mV, with a power consumption of only 12.6 nA. Over a temperature range of −40 °C to 120 °C, the temperature coefficient is 7.65 × 10−6/°C, with a linear regulation rate of 0.173% across a supply voltage range of 0.8–2 V, and a power supply rejection ratio of 68.02 dB@10 Hz.

A discrete frequency hopping oscillator fabricated using 0.18 m BCD process. This frequency hopping expands the Buck's fixed switching frequency to 9 discrete and close frequencies in the frequency range (92.5%fSW, 107.5%fSW), and the frequency hopping is performed every 16 switching cycles. The final complete frequency hopping period is 256 switching cycles. The additional low-frequency ripple introduced by this frequency hopping technique is only 3.14% of the switching ripple itself, while the EMI optimization effect reaches 11.94 dB; compared with the additional low-frequency ripple introduced by the conventional Spread-Spectrum technique, which is 11.3%, and the EMI optimization effect, which is 13.87 dB, the present technique achieves a good trade-off between the EMI optimization and the low-frequency ripple suppression.

To address the single-event triple-node upsets (TNUs) problem caused by charge sharing in latch circuits, this study proposes a TNU-hardened latch design, named LC-TNUTLD. The latch comprises two components: a latch module and an interception module. The latch module features two independent feedback loops, each composed of four CGE elements. The interception module employs a two-stage interception structure comprising three C elements. Design techniques such as high-speed signal paths, clock-controlled gating, and transistor minimization are employed to maintain performance while reducing the design cost. Simulation results show that the proposed latch significantly reduces the circuit area, power consumption, average delay, and power-delay product. At a clock frequency of 500 MHz, the circuit uses 48 transistors, consumes only 0.21 W, and achieves an average delay of 19.70 ps. Additionally, process, voltage, and temperature variation simulations and Monte Carlo analyses indicate that the LC-TNUTLD is robust against environmental and process fluctuations.

A bandgap reference (BGR) voltage source with low temperature drift and high power supply rejection ratio (PSRR) is designed based on the SIMC 0.18-m CMOS process. By applying the segmented compensation technique to optimize the temperature coefficient of BGR and introducing a pre-stabilization technique, the PSRR performance is significantly improved. Simulation results show that the temperature coefficient of the BGR is 1.3×10−6/℃ at the typical process corner. Across all process corners, with temperatures ranging from −40 ℃ to 125 ℃, the worst-case PSRR obtained is −131.7 dB.

A low-noise negative voltage low dropout linear regulator (LDO) based on BCD process was presented. Effect of high input voltage and noise on the circuit was analyzed. Most circuits worked under inner low-voltage region obtained by pre-stabilization circuit, which save the area and ensure the reliability of the circuit. Low pass filter was used to filter reference, which reduce the output noise. The LDO with a core chip area of 800 m×1050 m was taped out. The test results showed that maximum load current of 600 mA was provided by the LDO, under the dropout voltage of 250 mV. The noise was about −110 dBV/Hz at 1 KHz with load current 500 mA, when the input voltage was −6 V and the output voltage was −5 V.

Superconducting chips represent one of the most promising technological pathways toward realizing scalable, universal quantum computers owing to their strong compatibility with semiconductor fabrication processes, high scalability potential, and ease of qubit manipulation, readout, and coupling. In recent years, substantial progress has been made in enhancing decoherence times, gate fidelity, and medium-scale expansion within the field of superconducting quantum technology. However, as the number of qubits continues to grow, large-scale qubit integration has become increasingly critical. This paper analyzes key integration technologies, including flip-chip bonding, through-silicon vias, and "3D" stacking techniques, for superconducting quantum chips. It also discusses the main technical challenges that must be addressed. Finally, the paper offers an outlook on the development trends of these integration technologies.

For the problem of interconnect capacitance extraction in integrated circuits, the Local Discontinuous Galerkin (LDG) method-based extraction algorithm offers high accuracy, excellent parallel efficiency, and compatibility with various mesh types. Adaptive methods can further optimize the distribution of mesh elements, thereby reducing mesh elements and improving computational accuracy. This study proposes an adaptive LDG method for capacitance extraction that employs a posteriori error estimation. By accurately refining elements with large errors, the method generates an optimized adaptive mesh that reduces mesh elements and computational storage requirements while maintaining high accuracy. Multiple test cases involving single and multiple dielectrics verify the effectiveness of this method and demonstrate its advantages in convergence speed and storage efficiency over LDG methods with uniform mesh refinement and continuous finite element methods with adaptive mesh refinement.

An effective impact ionization rate model was first proposed by W. Fulop, which simplified the analytical processes for power semiconductor devices. However, this silicon-based model at room temperature is no longer applicable for modern device designs as it does not consider precision, new materials, and wide temperature ranges. Therefore, based on the effective impact ionization rate model, this study proposes a new temperature-dependent improved Fulop model, referred to as the TIF model. Using a p+-n abrupt junction as the research object and relying on an accurate unified impact ionization rate model, fitting expressions for the TIF model in Si, 4H-SiC, and GaN are obtained through MATLAB numerical fitting. Furthermore, analytical expressions for the p+-n abrupt junction based on the TIF model are successfully derived. The analytical results show good agreement with simulation results obtained using the MEDICI simulator, with a relative error of less than 2%.

To improve the measurement accuracy of thermoelectric microwave power detection, this study proposes a MEMS microwave power detection chip based on a seesaw structure. By integrating a cantilever beam in the form of a seesaw structure into the thermoelectric detection chip, a DC voltage is generated to represent the input microwave power. This approach reduces susceptibility to interference from peripheral circuits and noise, thereby enhancing the accuracy of microwave power signal detection. A sensitivity model for the thermoelectric microwave power detection chip is developed, and the effects of substrate etching depth and thermocouple length on chip sensitivity are analyzed. Measurement results show that the chip achieves a return loss better than −27 dB across the 8–12 GHz frequency range, demonstrating excellent microwave performance. The measured thermoelectric sensitivities are 2.2 V/W@8 GHz, 2.9 V/W@10 GHz, and 1.7 V/W@12 GHz. The proposed seesaw-structured microwave power detection chip significantly improves signal measurement accuracy. The findings provides a valuable reference for the design of thermoelectric MEMS microwave power detection chips.

Based on the traditional planar gate 4H-SiC VDMOS structure, a 2 000 V VDMOS with double P-type buried layer terminal structure was designed and optimized according to the field-limited ring theory. The influence of P-type buried layer parameters and P-shaped body area doping concentration on its breakdown characteristics is investigated. After the simulation and optimization of various parameter, the breakdown voltage reaches 2 860 V, which is 90.7% higher than that of the traditional 4H-SiC VDMOS. The maximum peak value of the surface electric field is 3.26×106 V/cm, the electric field distribution is uniform, the terminal utilization is high, the effective length is only 15 m, and no additional complicated technology is added, and it is easy to realize.

To alleviate the electric field peak issue at the bottom of the SiC UMOSFET gate and optimize the trade-off between breakdown voltage (BV) and specific on-resistance (Ron, sp), a 4H-SiC superjunction UMOSFET structure incorporating a high-k gate dielectric and P-shielding region (Hk SiC SJ UMOS) was investigated using the Sentaurus TCAD simulation software. In this structure, a P-shielding layer is introduced at the trench bottom to reduce the gate electric field. Through multiple epitaxial growths and high-energy ion implantation, two segments of P-pillars with varying concentrations are formed, creating a superjunction structure that effectively reduces specific on-resistance while maintaining high breakdown voltage. Furthermore, the high-k gate dielectric layer promotes a more uniform electric field distribution and increases surface charge in the drift region, further lowering the specific on-resistance. Simulation results indicate that, compared to conventional SiC UMOSFET structures, the superjunction variant without the high-k dielectric (SiC SJ UMOS) improves breakdown voltage by 23.4% and reduces on-state resistance by 14.6%. The Hk SiC SJ UMOS structure enhances breakdown voltage by 27.8% and lowers on-state resistance by 31.1%. Its figure of merit is approximately 2.37 times higher than that of the conventional structure, demonstrating superior electrical performance.

Cross-shaped horizontal Hall devices and three-contact, four-folded vertical Hall devices are commonly used in three-axis Hall sensors owing to their high symmetry, sensitivity, and low offset voltage. These configurations eliminate the Hall offset voltage of the devices through spinning current techniques. This study employs the Sentaurus TCAD 3D simulation and theoretical modeling to investigate sensitivity variations in these devices under different voltage and current bias conditions. Simulation results show that the cross-shaped Hall devices exhibit optimal correlation sensitivity at an aspect ratio (L/W) of 0.8–1.2 under current bias and 0.3–0.5 under voltage bias conditions, respectively. For three-contact, four-folded Hall devices, as the distance between contact electrodes increases, sensitivity increases until saturation under current bias conditions, whereas sensitivity continues to decline under voltage bias conditions. Additionally, increasing the P+ layer improves device sensitivity, and applying a four-phase spinning current method significantly reduces the offset voltage.

The junction termination design is crucial for high-power IGBT devices since it significantly affects the breakdown voltage and reliability of the device. The voltage resistance and stability of the IGBT are enhanced using a novel variation of lateral doping (VLD) termination structure, based on the buried layer (BL) and multiple field plate (multi-FP) designs. The structural parameters are optimized to analyze the correlation between the breakdown voltage and these parameters. This improves the internal electric field distribution within the termination structure. Consequently, the withstand voltage and avalanche ruggedness is increased. A breakdown voltage of 1650 V is achieved at a terminal length of 340 m. The maximum surface electric field is 1.64×10⁵ V/cm. Notably, the devised terminal structure did not exhibit the snapback phenomenon under the overvoltage conditions and maintained a positive differential resistance (PDR) state during the post-avalanche states, indicating excellent avalanche robustness.

Aiming at the problems of high cost and low analog output frequency of existing audio signal sources, which cannot meet the performance requirements of newly developed ADC testing, this paper designs a high signal-to-noise ratio and low distortion analog signal source system based on coarse and fine weight voltage calculation. The signal source system utilizes four high-resolution analog-to-digital converters to form a high-purity, high-resolution differential analog signal source after superposition and operation. An experimental module circuit of the signal source system is made according to the principle and structure of the signal source system. The output performance of a single DAC analog signal source and the four-DACs analog signal source is tested by a high-resolution ADC evaluation platform. The test results show that the analog signal source after four DACs are stacked has the characteristics of low cost, low offset, low harmonic distortion, and high signal-to-noise ratio.

Automated optical inspection (AOI) of integrated circuits mainly has four NG misjudgment problems—mark recognition, offset detection in panel products, poor solder joints, and incorrect chip polarity. Aiming to mitigate these problems, this study analyzes their root causes and proposes improvement measures—mark graphics selection and optimization, the matching of panel mark settings and operation logic, the combined optimization of solder joint detection algorithm, and the matching of polarity detection algorithm and chip characteristics, respectively. Statistical data show that the implementation of these improvements significantly reduces NG misjudgments and greatly enhances AOI detection performance.

Power MOSFETs are widely employed in power switching applications owing to their high switching speeds. However, the heat generation during switching makes thermal resistance a critical factor, directly impacting device reliability. This study applies K-factor calibration according to JEDEC JESD 51-1 and JESD 51-14 standards and measures both junction-to-case and junction-to-ambient thermal resistances under steady-state and transient conditions. The steady-state junction-to-case thermal resistance is determined using the dynamic electrical and transient dual-interface methods. Heating characterization tests yield transient heating curves, differential structure functions, and cumulative structure functions. These results are used in thermal structure analyses to segment the internal physical layers and to develop four-stage Cauer and Foster network RC thermal models.