In this study, a high-precision capacitive sensing chip is designed using a 180-nm 1.8-V CMOS process. The chip employs a discrete-time second-order chain of integrators with weighted feed-forward summation (CIFF) structure Sigma-Delta modulator as the front-end circuit for capacitive detection. Techniques such as chopper-stabilized differential amplifiers, gate-bootstrapped switches, and lower plate sampling are utilized to enhance the accuracy of capacitance measurement. The overall circuit is simulated using software, and the results indicate that the capacitive sensing circuit can accurately detect capacitances ranging from 0 to 32 pF. At a measurement frequency of 10 Hz, the chip achieves an absolute capacitance resolution of approximately 10 aF. The core circuitry of the capacitive sensing chip is fabricated, and appropriate testing environments are established to conduct post-fabrication testing and validation. The testing setup employed instruments such as oscilloscopes, and the results demonstrate that the chip has a capacitance detection range of 0 to 32 pF. At a conversion frequency of 100 Hz, the absolute capacitance resolution is approximately 1 fF, whereas at a conversion frequency of approximately 6 Hz, the absolute capacitance resolution can reach 35 aF.