Gate oxide interface traps are the primary cause of reliability degradation in SiC MOSFETs. In this study, based on the structure of N-type 4H-SiC MOSFETs, the impact of gate oxide interface traps on the electrical characteristics and reliability of the devices under bias temperature stress was systematically investigated. The research results indicated that the density and energy levels of acceptor traps significantly affected the electrical characteristics, specifically manifested as a positive shift in the threshold voltage, an increase in the on-resistance, and changes in the C-V characteristic curves. The influence of donor traps on the electrical characteristics was relatively minor, primarily reflected in the capacitance changes in the accumulation region of the C-V curves. At high temperatures, the carrier capture capability of shallow-level acceptor traps significantly weakened; however, deep-level acceptor traps maintained a strong capture capability. Additionally, the hot carrier injection effect was related to the magnitude and duration of the gate stress. Increasing the gate bias and stress time led to an increase in the interface trap density and their range expands, affecting the electrical characteristics of the device and significantly degrading long-term reliability.