To address the application requirements of quasi-cyclic low-density parity-check (QC-LDPC) codes in 5G new radio (NR) systems, we propose an encoding optimization method based on cyclic reconstruction of generator submatrices. This method determines the base matrix, lifting factor (Z), and generator submatrix (P) according to the code length and code rate of the input information sequence. By storing and reconstructing the generator submatrix at intervals of Z, the method effectively reduces memory resource consumption. The encoder is implemented and verified on a field programmable gate array (FPGA) platform using Verilog HDL. The results show that the optimized design reduces look-up table (LUT) resource consumption by 14.6% and register resource consumption by 54.6% compared with direct encoding, and the maximum encoding throughput can reach 2.7 Gb/s at a clock frequency of 100 MHz, which can satisfy the application requirements of high-speed coding.