Microelectronics, Volume. 55, Issue 4, 549(2025)

65-nm CMOS Low-phase-noise and Low-power Voltage-controlled Oscillator Circuit

LI Tiehu, ZHANG Wei, GUO Chaodong, HUANG Jintao, ZENG Jun, and ZHANG Jun'an
Author Affiliations
  • School of Artificial Intelligence, Chongqing University of Technology, Chongqing 401135, P R China
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    This paper introduces a voltage-controlled oscillator (VCO) with low phase noise and low power consumption, implemented using a 65-nm CMOS technology. The design features a resonator with dual cross-coupled PMOS transistors and an AC-coupled variable capacitor, reducing VCO gain and significantly improving phase noise. Moreover, the design incorporates six sets of switchable capacitors to broaden the tuning range of the oscillator, resulting in a wide frequency spectrum while preserving low phase noise. Post-simulation results show that at a supply voltage of 1.2 V, the VCO consumes 3.49 mW and has an oscillation frequency range from 4.78 to 5.24 GHz. At an output frequency of 4.90 GHz, the phase noise measures −128.66 dBc/Hz at a 1 MHz offset, and the root mean square jitter is 425.85 fs. This low-noise, low-power, wide-bandwidth VCO is ideal for high-precision clocks, wireless systems, and high-speed data converters requiring quality clock signals.

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    LI Tiehu, ZHANG Wei, GUO Chaodong, HUANG Jintao, ZENG Jun, ZHANG Jun'an. 65-nm CMOS Low-phase-noise and Low-power Voltage-controlled Oscillator Circuit[J]. Microelectronics, 2025, 55(4): 549

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    Paper Information

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    Received: Sep. 3, 2024

    Accepted: Sep. 9, 2025

    Published Online: Sep. 9, 2025

    The Author Email:

    DOI:10.13911/j.cnki.1004-3365.240301

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