For H-shaped gate Double Silicon-On-Insulator (DSOI) NMOS devices, a difference in Total Ionizing Dose (TID) response has been observed with varying channel widths. Devices with wider channels exhibit more significant degradation in electrical parameters. By studying the trap charge density using the Subthreshold Current technique and Direct Current-Voltage technique, the results indicate a positive correlation between channel width and oxide trap charge density, while the interface trap charge density decreases as channel width increases. The variation in the electric field among devices with different channel widths under TG bias is identified as the primary cause of the different radiation-induced oxide trap charge densities. Additionally, the accumulation of oxide trap charge, which forms an electrostatic barrier, influences the generation of interface trap charges.

The study investigated the impact of leakage degradation caused by heavy ions on the gate reliability of 1 200 V SiC MOSFETs. The results showed that under Ta ion irradiation, when VDS was between 150 V and 200 V, the device's leakage current increased from nanoamperes to microamperes. Emission Microscope (EMMI) analysis revealed that the damage was primarily concentrated in the main junction region of the device. After 168 hours of testing at a 20 V gate voltage, the gate leakage current of the degraded device increased from a few microamperes to hundreds of microamperes. However, the maximum transconductance and transfer characteristics did not change significantly. The experiment also confirmed that under negative gate voltage irradiation conditions, the device gate was more susceptible to leakage. In summary, this study provides new insights into the evaluation of gate reliability and the enhancement of radiation hardness for SiC MOSFETs after irradiation, offering valuable perspectives for simulating heavy ion single-particle effects relevant to both space and ground environments.

Simulation studies were conducted to investigate the effects of heavy ions with different LET values incident at varying orientations and angles on FinFET SRAM. The study found that the upset state of FinFET SRAM is significantly affected by the ion incident direction. Incidence along the fin is more likely to cause the SRAM cell to upset, while incidence perpendicular to the fin is less likely to cause upset. When the LET value of the ions is low or the angle is large, the charge generated by ionization from ions incident on the sensitive drain is insufficient to cause the SRAM cell to upset. However, when the LET value of the ion is high and the angle of incidence is within a certain range, the ion penetrates through the fin of the N-FinFET, affecting the N-well and triggering the parasitic bipolar effect. When the LET value is sufficiently high, the parasitic bipolar current exceeds the current caused by the drain drift collection mechanism, leading to single event upset recovery. The results of this study provide valuable insights for the radiation hardening of FinFET integrated circuits.

Due to their characteristics of high frequency, low noise, low power consumption, and high gain, InP-based High Electron Mobility Transistors (HEMTs) show great potential in space high-frequency signal receiving systems. To enhance the application of InP-based HEMTs in space radiation environments, a study was conducted using two-dimensional simulations to investigate the effects of particle incidence position, temperature, and incidence angle on single event transients (SETs) in InP-based HEMTs. The results indicate that different incident locations have varying impacts on peak drain current and collected charge, with the gate position exhibiting the highest sensitivity to SETs, resulting in the largest peak drain current and collected charge. As the incident angle increases, more holes are generated in the buffer layer, leading to a reduction in the potential barrier under the gate, which in turn increases both the peak drain current and pulse width. Conversely, an increase in temperature leads to a decrease in electron mobility within the channel, reducing both peak drain current and pulse width. When considering the combined effects of temperature and particle incidence angle, it is evident that temperature significantly influences the peak drain current generated by small-angle incidence. This research provides a theoretical foundation and practical guidance for designing InP-based HEMTs that are resilient to SETs in space applications.

Ultra-high-speed analog-to-digital converters (ADCs) are key components in signal processing units such as phased array radars and digital multi-mode receivers. However, their accompanying systems are susceptible to single event effects (SEE) caused by cosmic ray irradiation in space, leading to device performance degradation and, in severe cases, functional interruption. This project analyzes and studies the mechanisms of single event effects in streamlined ADCs. It proposes a ground simulation testing method for single-event latch-up (SEL), single-event upsets (SEU), and single-event transients (SET) in ultra-high-speed ADCs (≥3 GS/s). A single event effects online testing system for ultra-high-speed ADCs is implemented using CER detection principles and high-speed code value anomaly handling methods. Experimental verification was conducted at the HI-13 and HIRFL facilities, where typical single event test effects, such as SEL, SEU, and SET, were successfully monitored. Finally, a single event effect analysis of the circuit was conducted based on experimental data and circuit structure. The evaluation and application stage system verification of high-speed ADC integrated circuits is of great significance.

High-speed digital-to-analog converters (DACs) are core components of microwave return systems and radar jammer signal processing units. In the aerospace environment, they are highly susceptible to radiation, which can lead to functional abnormalities. Due to their extremely high interface data rate, evaluating single-event functional interrupts (SEFI) presents significant challenges. This study investigates and analyzes four types of single-event functional interruptions in high-speed DACs in heavy ion environments. A single-event functional interrupt ground simulation testing method for JESD204B interface DACs (≥12 GS/s) is proposed. Additionally, a single-event functional interrupt online testing system for JESD204B interface digital/analog converters, based on the current steering structure, is designed and implemented. Experimental verification was conducted at the HI-13 and SESRI facilities, successfully monitoring the single-event functional interrupt phenomena, which were consistent with the device structure mechanism analysis. This work provides valuable guidance for subsequent reinforcement design.

SiC Schottky barrier diodes (SiC SBDs) are highly attractive for aerospace applications due to their low power consumption, high temperature tolerance, and high switching frequency. However, their resistance to single-event burnout (SEB) remains significantly below expectations. The SEB effect of a 1 200 V silicon carbide trench junction barrier Schottky (TJBS) diode was investigated using two-dimensional numerical simulations. The results revealed that the peak temperature distribution varies depending on the location of particle incidence. The single-event sensitive regions were identified as the P+/n− and n−/n+ junctions. To enhance the SEB resistance of these sensitive areas, a novel structure featuring a stratified P region and a Gaussian buffer layer was proposed, termed the SP-TJBS. Compared to the conventional TJBS structure, the peak temperature of the SP-TJBS structure is only 44.6% of that of the TJBS diode when ions hit the center of the Schottky junction, and it is only 52.2%–56.3% when ions hit the P+ region, demonstrating excellent single-event burnout resistance.

A radiation-hardening, wide-input-range bandgap reference is designed based on the study of the degradation mechanism of bandgap reference circuits in radiation environments. The design enables the circuit to operate at higher voltages by establishing internal power rails and uses the fork-finger structure of MOS devices to effectively isolate the Shallow Trench Isolation (STI) region from the active region, thereby hardening the reference core against Total Ionizing Dose (TID). Additionally, a Dynamic Load Tracking (DLT) technique is proposed to address the effects of Single Event Transients (SET) on the reference circuit. The output filtering, pass transistor gate filtering, and DLT technique are all applied to enhance SET resilience. The circuit is designed using a 0.18 m 40 V BCD process, and simulation results show that the circuit can operate within a voltage range of 6 to 40 V. The PN junction current variation of the forked-finger structure under maximum trapped charge concentration is reduced by 27% compared to that of the single-finger structure, and the SET pulse amplitude is reduced by 80% compared to the non-hardened design.

Based on a thick-film hybrid integrated anti-radiation forward DC/DC converter, this paper studies the design of magnetic components and magnetic isolation feedback methods. The developed anti-radiation forward DC/DC converter, which converts an 18 V–36 V input voltage to a 28 V/4.3 A rated output with a maximum conversion efficiency of over 87%, demonstrates the ability to resist total dose and neutron radiation.

To address the differences in total ionizing dose (TID) effect failure modes and failure doses of commercial microprocessors with varying feature sizes, an experimental study was conducted using microprocessors with 180 nm, 90 nm, and 40 nm feature sizes from the same manufacturer. A laboratory-developed, extendable online test system for assessing the TID effect of microprocessors was employed to monitor the status of communication, digital-to-analog signal conversion, non-volatile memory, random-access memory, direct memory access, consumption current, clock, and timers during the 60Co irradiation experiment. The results indicate that the error doses for the three microprocessors are 331±36.28 Gy(Si), 355.5±41.51 Gy(Si), and 365.28 ± 20.15 Gy(Si), respectively. The failure models vary according to the feature sizes of the tested microprocessors. Specifically, the 180 nm microprocessor's most radiation-sensitive unit is the on-chip non-volatile memory, whereas for the 90 nm and 40 nm microprocessors, the device cores are the most radiation-sensitive units.

Low dose rate irradiation experiments were conducted on Lateral-PNP transistors fabricated using the same process to investigate the enhancement effects of low dose rate radiation damage in bipolar transistors with different perimeter-area ratios (P/A), base effective widths, emitter areas, and oxide layer thicknesses. Experimental results show that the gain of the Lateral-PNP bipolar transistor before and after irradiation is reduced by less than 50% at low dose rates, with the gain remaining greater than 100 after irradiation. The results indicate a significant improvement in the radiation resistance of the Lateral-PNP transistor through increases in the perimeter-area ratio (P/A), reduction of the base effective width, expansion of the emitter area, and thinning of the oxide layer thickness.

Total dose effects on SiGe-on-SOI HBT were studied using semiconductor device simulation tools. STI and EB spacer oxide trap charges and interface trap charges cause additional base leakage current, leading to degradation of electrical parameters in SiGe-on-SOI HBT devices. The excess base currents and normalized current gain under different bias conditions and low-temperature conditions were analyzed. The results show that the degradation at cutoff bias is the worst, followed by zero bias, while forward bias and saturation bias exhibit better anti-radiation performance. At low-temperature conditions, the initial generation rate and transport time of electron-hole pairs in the oxide layer decrease; oxide-trap charges and interface states are reduced due to the decrease in recombination current, so Gummel characteristics are significantly improved. After total dose irradiation of 1 Mrad (Si), fT and fmax increased by 10% and 8%, respectively. The RF characteristics are improved by the TID. This work provides a reference for the development and application of SiGe-on-SOI HBT aerospace devices.

This paper uses Synopsys Sentaurus TCAD to study single-event transients (SET) in 22 nm Fully-Depleted Silicon-On-Insulator (FDSOI) devices. The study first explores the impact of different LET values on SET characteristics. The results indicate that as LET increases from 10 MeV·cm2/mg to 35 MeV·cm2/mg, the peak transient current rises from 180 A to 700 A, and the pulse width extends from 10 ps to 13 ps, demonstrating the significant impact of higher LET values on single-event transients. The study also investigates the effect of different incident positions. When the single particle hits the source, gate, and drain electrode centers, the collected charges are 1.12 fC, 5.41 fC, and 2.22 fC, respectively. The gate collects the most charge, indicating it is the most sensitive area. Finally, the study examines three different bias voltages. In the off state, the devices exhibit the highest transient current (190 A) and pulse width (16 ps), reflecting the most significant impact on single-event characteristics.

A highly reliable startup circuit based on current sampling and MOS switching is proposed to address the startup issues of a no-ground-on-chip three-terminal voltage regulator. A low-voltage design strategy was adopted, enabling a low dropout voltage. The circuit was designed and simulated using the CSMC 0.25 m 60 V BCD process, and successfully underwent tapeout and testing. Simulation results showed that after implementing the proposed startup circuit scheme, the voltage regulator could start stably. The dropout voltage range of the regulator is 1.35 V to 35 V, and the maximum output current is 7.5 A. The temperature coefficients of the reference voltage and output voltage are 1.13×10-5/℃ and 1.22×10-5/℃, respectively. The voltage regulator exhibits good linear regulation and load regulation. Test results indicate that the designed high-reliability startup circuit enables the voltage regulator to start normally when powered on.

A low-power, low-phase-noise fractional-division phase-locked loop (PLL) based on a 65 nm CMOS process is designed. To suppress the quantization noise introduced by the Delta-Sigma Modulator (DSM) in the fractional-division PLL, this paper combines three strategies: increasing the DSM operating frequency, reducing the quantization step size, and phase-domain filtering. The first stage employs a conventional integer PLL to provide 16 phases and realizes fractional frequency doubling through DSM-based phase selection. The second stage uses an injection-locked oscillator to further multiply the frequency and filter out DSM quantization noise. Circuit simulation results show that the power consumption is 8.42 mW at a 1.2 V supply voltage. The input reference frequency is 50 MHz, and the input decimal control word is equivalent to 0.968. The lock time is 1.5 s, the output frequency is 1.936 GHz, and the frequency range is 1.128–1.936 GHz. The overall output phase noise at a frequency deviation of 1 MHz is -107.3 dBc/Hz, and the peak quantization noise is −126 dBc/Hz.

A switching power supply can be classified as either an isolated or non-isolated power supply, based on the presence of electrical isolation. An isolated power supply uses devices in the power transmission and signal feedback paths to provide electrical isolation, thereby protecting against ground loops and power supply failures. Traditional isolated power supplies utilize linear optocouplers, which face limitations such as limited bandwidth and aging. To address these issues, this paper proposes the design of an isolation error amplifier based on a high-voltage capacitor to close the isolation feedback loop. PWM and OOK modulation are used to enable analog signal transmission across the isolation barrier, offering the advantages of high integration and CMTI. The operational principles of the proposed isolation error amplifier and the modulation/demodulation process are analyzed in detail. The proposed chip is designed using a 0.18 m BCD process. Simulation results demonstrate that the isolation error amplifier can support error voltage transmission of 1x and 2.6x when the output voltage of the isolated power supply is between 4 and 40 V, which is used to drive the PWM controller.

During the conversion phase, the CDAC’s output voltage in the SAR ADC must be maintained within the range of GND and VDD. Otherwise, the switch connected to this node cannot effectively turn off, and the charge in the CDAC cannot be conserved during the quantization period. By analyzing the quantitative relationship among the output voltage of the CDAC, the input signal, Vcms (sampling common mode), and the reference voltage, a design concept of a variable common mode has been adopted for large input range monitoring applications. This approach solves the above issues and avoids the need for complex input driver circuits. A 14-bit synchronized SAR ADC with 1 kS/s is designed based on a 500 nm process. Post-simulation results show that the proposed ADC can achieve an ENOB of 13 bits.

This paper presents a low-power, high-precision oversampling SAR ADC circuit fabricated using 65 nm CMOS technology. It analyzes the impact of DAC mismatch and comparator noise on ADC performance and employs a second-order CIFF passive integration and mismatch error shaping technique to significantly reduce in-band noise and harmonics, as well as mitigate the effect of CDAC capacitor array mismatch. Additionally, an analog three-level prediction scheme is proposed to address the dynamic range loss caused by MES. The SAR ADC circuit achieves an SNDR of 87.4 dB, a power consumption of 95 W, and an FoM value of 183.8 dB at a 10 MS/s sampling clock and an oversampling ratio of 12.

The effective resolution of successive-approximation (SAR) analog-to-digital converters (ADCs) is primarily limited by sampling noise, analog-to-digital converter (DAC) mismatch, and comparator noise. This work presents a noise-shaping SAR ADC design that addresses all of these error sources. Sampling noise is mitigated using a kT/C noise cancellation technique combined with resampling. DAC mismatch is managed through data-weighted averaging (DWA) and mismatch error shaping (MES), while comparator noise is reduced using a second-order passive noise-shaping (NS) technique. Designed in a 40 nm CMOS process, the simulation results show that the ADC achieves an 86.8 dB signal-to-noise and distortion ratio (SNDR) across a 2.8 MHz bandwidth with a power consumption of 3.8 mW.

Conventional charge pumps cause ripple in the output voltage due to current mismatch, which negatively impacts the noise and spurious performance of the PLL. A digital calibration technology and output impedance enhancement structure with high static current match was designed to achieve dynamaic mismatch calibration. Based on the source switch structure, the design overcomes the non-ideal effects of clock feedthrough and charge sharing, and utilizes an operational amplifier to clamp the voltage and eliminate the mismatch caused by channel length modulation effects in the output voltage. The mismatch relationship between the charging and discharging currents is inferred by detecting variations in the output voltage through a comparator. A digital calibration logic circuit and a compensation current circuit are designed to correct the determined mismatch current in the reverse direction, achieving calibration. The circuit is designed using a CMOS 55 nm process. Post-simulation results show that with a 1.2 V power supply, the output dynamic range of the 100 A current charge pump is 0.22–1.06 V, with a static current mismatch of less than 0.12%. The calibration function reduces the dynamic mismatch from 2.4 A to 0.27 A, and the chip area is 0.039 mm2.

This paper proposes a dual-loop digital-assisted analog low-dropout linear regulator (LDO) circuit architecture suitable for digital loads. The digital logic controller adopts a hybrid algorithm for segmentations and binary searches. When a transient event occurs, the digital loop control is mainly used to conduct quick searches and determine the number of power tube groups that are turned on, provide coarse current adjustment, and achieve a fast transient response. It then enters the steady state and mainly uses analog loop control to provide fine current adjustment to achieve high-precision DC voltage output. The proposed hybrid LDO is designed based on a 55 nm CMOS process, has a maximum load capacity of 52 mA, and the working clock of the digital logic controller is 50 MHz. The simulation results show that when the load current changes between 2–52 mA within 200 ns, the maximum overshoot voltage and overshoot voltage of the hybrid LDO circuit are 121 mV and 154 mV respectively, and the transient recovery time is <1 s.

As process node advances and integrated circuits scale up, interconnect delay increasingly dominates total delay. Traditional reliance on timing analysis tools for calculating interconnect delays during physical implementation hinders design completion speeds. We propose an interconnect delay prediction model based on LightGBM, aiming for both efficiency and accuracy. Unlike existing models that only focus on the parasitic parameters of interconnects, it also innovates by incorporating density features aware of routing resources and statistical global features that expand data dimensionality, employing the LightGBM model to achieve accurate predictions of interconnect delays. Compared to existing methods, our model significantly enhances prediction accuracy, reducing the overall mean absolute error to 0.452 ps—a 64.1% decrease in error. These findings confirm the effectiveness of the proposed method, providing a novel approach for interconnect delay prediction in physical design routing stage.

This paper presents a novel trench SiC power MOSFET device with an inherent self-biased PMOS for clamping the potential of the P-shield region at the bottom of the gate trench. The integrated PMOS has the P-shield region at the bottom of the trench serving as the source, the P+ source region as the drain, and the source metal filling the trench acting as the gate, with the gate and drain being short-circuited. By utilizing the clamping effect of this PMOS, the potential of the P-shield region at the bottom of the gate trench can be regulated. When the device is on, the PMOS is cut off, allowing the P-shield region to float, thereby improving the JFET effect in the channel region of the SiC MOSFET and reducing the specific on-resistance (Ron, sp) of the device. When the device is under high drain voltage, the self-biased PMOS turns on, clamping the potential of the P-shield region, thus enhancing the electric field shielding effect of the P-shield region on the gate oxide layer and improving the reliability of the device. Simulation results show that the proposed device has a breakdown voltage (BV) of 1 430 V and a Ron, sp of 1.70 m&#x2027;cm2, exhibiting comparable BV and improved Ron, sp compared to conventional devices. The gate-drain charge and high-frequency figure of merit are enhanced by more than 14.3% and 20%, respectively. Additionally, the proposed device has a lower gate oxide E-field than conventional devices.

A bidirectional SCR device (LCDDSCR) with low trigger voltage and low capacitance has been designed to meet the increasing demands of system design for ESD protection, particularly in relation to the transmission rate and signal frequency of data interfaces, based on a 0.5 m BCD process. Compared to the conventional bi-directional SCR device structure (DDSCR), the LCDDSCR structure employs the critical diffusion technique to reduce the area of the P-well region, thereby lowering the device's input capacitance. Additionally, the ZP region is introduced using the critical Zener injection technique to reduce the trigger voltage, based on the Zener triggering characteristics of the SCR device. Transmission line pulse (TLP) test and capacitance test results show that the LCDDSCR device has a trigger voltage of 7.5 V, a sustaining voltage of 1.5 V, a junction capacitance of 0.53 pF, and a peak inrush current of 7 A (0.53 pF/7 A), which satisfies the requirements for ESD protection and exhibits excellent low capacitance and low trigger voltage characteristics.

A dual-channel microwave power detection chip based on MEMS cantilevers is proposed to improve the overload power of thermoelectric microwave power detection chips. By integrating a MEMS fixed-beam with the thermoelectric chip, the design not only protects the thermoelectric chip but also increases its overload power. Theoretical models are established for the capacitive and thermoelectric detection channels, and the sensitivity characteristics and overload power are studied. Test results show that the measured sensitivity of the capacitive channel is 2.21 fF/W, with a theoretical value of 2.24 fF/W, resulting in a theoretical model error of only 1.34%. The measured sensitivity of the thermoelectric channel is 0.03 mV/mW, which aligns with the theoretical value from the model. The overload power model indicates that the chip's overload power can reach 8.77 W. Therefore, compared to a single thermoelectric chip, the dual-channel chip not only achieves high-quality detection of both small and large power signals but also enhances overload power.

In this study, we implemented a square Hall device based on a 0.18 m Bipolar-CMOS-DMOS (BCD) process for high sensitivity and low offset. The magnetic sensitivity of the device is significantly improved by adopting the low-doped N-type drift layer as the active area and by using the buried P-type layer to reduce the thickness of the active area. Furthermore, we employed the static orthogonal coupling technique to reduce the output offset voltage. The tape-out test results indicate that the voltage-related sensitivity and current-related sensitivity of the proposed Hall device reach 4.14%V/(V·T) at a bias voltage of 3 V and 388 V/(A·T) at a bias current of 300 A, respectively. Furthermore, the output offset voltage is as low as 0.3 mV by utilizing the coupling structure, demonstrating good four-phase symmetry. The residual offset voltage can be further reduced to less than 6 V when the four-phase spanning current technique is applied.

The resolution of conventional time-domain reflectometry (TDR) is limited when applied to fault localization for defects smaller than 100 m, especially in high-density advanced packaging. The principle of electro-optical terahertz pulse reflectometry (EOTPR) is introduced, which uses femtosecond laser excitation to generate stable, fast pulses in the terahertz frequency range. These pulses are injected into the device under test, and the reflected signals are rapidly sampled using asynchronous electro-optic sampling, achieving a resolution of sub-65 m for failure localization. By utilizing EOTPR, rapid and accurate localization of failures, such as buried via fractures in wire-bonded BGAs, UBM fractures in FCBGAs, and through-hole fractures in MCM packages, has been achieved. This method provides the potential for three-dimensional failure localization in advanced complex packaging.