A low-power, low-phase-noise fractional-division phase-locked loop (PLL) based on a 65 nm CMOS process is designed. To suppress the quantization noise introduced by the Delta-Sigma Modulator (DSM) in the fractional-division PLL, this paper combines three strategies: increasing the DSM operating frequency, reducing the quantization step size, and phase-domain filtering. The first stage employs a conventional integer PLL to provide 16 phases and realizes fractional frequency doubling through DSM-based phase selection. The second stage uses an injection-locked oscillator to further multiply the frequency and filter out DSM quantization noise. Circuit simulation results show that the power consumption is 8.42 mW at a 1.2 V supply voltage. The input reference frequency is 50 MHz, and the input decimal control word is equivalent to 0.968. The lock time is 1.5 μs, the output frequency is 1.936 GHz, and the frequency range is 1.128–1.936 GHz. The overall output phase noise at a frequency deviation of 1 MHz is -107.3 dBc/Hz, and the peak quantization noise is −126 dBc/Hz.