In this study, we implemented a square Hall device based on a 0.18 μm Bipolar-CMOS-DMOS (BCD) process for high sensitivity and low offset. The magnetic sensitivity of the device is significantly improved by adopting the low-doped N-type drift layer as the active area and by using the buried P-type layer to reduce the thickness of the active area. Furthermore, we employed the static orthogonal coupling technique to reduce the output offset voltage. The tape-out test results indicate that the voltage-related sensitivity and current-related sensitivity of the proposed Hall device reach 4.14%V/(V·T) at a bias voltage of 3 V and 388 V/(A·T) at a bias current of 300 μA, respectively. Furthermore, the output offset voltage is as low as 0.3 mV by utilizing the coupling structure, demonstrating good four-phase symmetry. The residual offset voltage can be further reduced to less than 6 μV when the four-phase spanning current technique is applied.