Conventional charge pumps cause ripple in the output voltage due to current mismatch, which negatively impacts the noise and spurious performance of the PLL. A digital calibration technology and output impedance enhancement structure with high static current match was designed to achieve dynamaic mismatch calibration. Based on the source switch structure, the design overcomes the non-ideal effects of clock feedthrough and charge sharing, and utilizes an operational amplifier to clamp the voltage and eliminate the mismatch caused by channel length modulation effects in the output voltage. The mismatch relationship between the charging and discharging currents is inferred by detecting variations in the output voltage through a comparator. A digital calibration logic circuit and a compensation current circuit are designed to correct the determined mismatch current in the reverse direction, achieving calibration. The circuit is designed using a CMOS 55 nm process. Post-simulation results show that with a 1.2 V power supply, the output dynamic range of the 100 μA current charge pump is 0.22–1.06 V, with a static current mismatch of less than 0.12%. The calibration function reduces the dynamic mismatch from 2.4 μA to 0.27 μA, and the chip area is 0.039 mm².