During the conversion phase, the CDAC’s output voltage in the SAR ADC must be maintained within the range of GND and VDD. Otherwise, the switch connected to this node cannot effectively turn off, and the charge in the CDAC cannot be conserved during the quantization period. By analyzing the quantitative relationship among the output voltage of the CDAC, the input signal, V_cms (sampling common mode), and the reference voltage, a design concept of a variable common mode has been adopted for large input range monitoring applications. This approach solves the above issues and avoids the need for complex input driver circuits. A 14-bit synchronized SAR ADC with 1 kS/s is designed based on a 500 nm process. Post-simulation results show that the proposed ADC can achieve an ENOB of 13 bits.