An innovative 10-bit segmented current-steering digital-to-analog converter (DAC) was designed through an SMIC 180 nm standard CMOS process, utilizing a minimalistic footprint of 320 μm×150 μm. The "5+5" segmentation architecture achieves a high-position quantization ladder of the DAC through resistors, thus minimizing the total current. Compared with the original resistance quantization structure, this innovative structure alters the current flow direction, conserving half the current sources. Furthermore, the distinct non-ideal characteristics inherent in this novel structure are rectified effectively using a calibration method, traditionally employed in resistor string DACs. Simulation results show that the differential nonlinearity (DNL) and integral nonlinearity (INL) of the DAC are confined to 0.09 and 0.34 LSB, respectively, while achieving a spur-free dynamic range of 64.52 dB and a power consumption of 8.58 mW. Compared with conventional structures, this structure demonstrates an approximate 80% reduction in the area consumption and mitigates the power and area of the segmented current-steering DAC.

Aiming at first-order noise shaping (NS), which often compromises power consumption to achieve a high effective number of bits (ENOB) and oversampling rate (OSR), this study proposes a second-order passive NS SAR ADC with a low OSR and low power consumption, whose higher passive gain can better suppress the noise of the comparator, and the residual voltage is achieved by multiplexing the integrating capacitors through the switching MOS array. Thus, the generation of the residual sampling capacitance clearing and residual sampling kT/C noise is avoided, reducing the total kT/C noise. Based on a 180 nm CMOS process, the simulation results show that without digital calibration, the designed 10-bit second-order passive NS SAR ADC circuit achieves an ENOB of 13.5 bits at a sampling rate of 100 kS/s with an OSR of 5. The power consumption is 6.98 μW.

Based on a 180 nm CMOS process, a sigma-delta continuous-time modulator with reconfigurable feedforward third-order operation was designed for audio applications. The traditional sigma-delta continuous time modulator has only one operating mode, but the proposed modulator with the reconfigurable integrator has two operating modes: high-resolution and low-power consumption modes. In addition, summation ahead is used to reduce the power consumption of the modulator, negative-R compensation is used to improve the SNDR of the modulator, and excess loop delay compensation is used to improve the stability of the modulator. With a signal bandwidth of 20 kHz and supply voltage of 1.8 V, the modulator has an SNDR of 94.7 dB and power consumption of 291 μW in the low-power consumption mode and an SNDR of 108 dB and power consumption of 436.6 μW in the high-resolution mode.

A two-stage, low-power, wideband low noise amplifier (LNA) was designed using a 65 nm CMOS process to address the requirements of wireless local area network (WLAN) devices for Wi-Fi 6 and Wi-Fi 6E (5GHz, 6 GHz) applications. The first stage of the circuit adopts a cascode structure, combining the complementary common-source circuits. By incorporating inductor peaking and negative feedback techniques, the input transconductance is enhanced, the noise is reduced, and the bandwidth is expanded, resulting in improved gain flatness. The second stage introduces an auxiliary amplification structure and an inductor peaking technique based on a common-drain buffer, which cancels out the noise from the first-stage common-source transistor and further extends the bandwidth. Both stages employ the proposed self-forward body biasing technique to reduce the circuit’s dependency on the power supply voltage. The overall circuit implements dual-current reuse to effectively lower the power consumption. The simulation results demonstrate that the LNA achieves S21 of 17.8±0.1 dB within the frequency range of 5-9.3 GHz, with S11 less than -9 dB, S22 less than -11.9 dB, and NF below 1.34 dB. The overall circuit power consumption is 5.3 mW at a voltage of 0.8 V.

Noise cancellation is a common technology in the design of low noise amplifiers (LNA). Solving the contradiction between noise and power consumption is the most difficult challenge during the design process. A new noise cancellation structure is proposed in this study. Noise in the main and auxiliary branches is eliminated by adding a feedback loop between the main and auxiliary branches, without increasing power consumption. Based on a 180 nm CMOS technology, a wideband low noise amplifier with the noise cancellation structure is designed.Simulation results show that the bandwidth of the LNA is 0.4-2.36 GHz, both S11 and S22 are less than -10 dB,S12 is less than -30 dB, the maximum S21 is 14.5 dB, the noise factor is 2.20-2.34 dB, and the power consumption is 9 mW.

A low-noise analog front-end circuit (AFE) was designed using UMC 28 nm CMOS technology for optical receivers operating at 80 Gbit/s PAM4. To address the tradeoff between the noise and bandwidth, we adopted a trans-impedance amplifier (TIA) cascaded continuous time linear equalizer (CTLE) and input inductor peaking. A VGA with trans-conductance and a trans-impedance (gm-TIA) structure was adopted to effectively control the low-frequency gain and further expand the bandwidth. The circuit achieves a trans-impedance gain of 48.5 dBΩ, a bandwidth of 36.1 GHz, an average equivalent input current noise of 22.6 pA/ Hz, and a power consumption of 14.5 mW, under the conditions of an input capacitance of 100 fF and a supply voltage of 1.2 V.

A high-PSR capless-LDO circuit with body-ripple injection based on 40 nm CMOS IC process was designed. The circuit is powered by a 1.1 V power supply, and the LDO output voltage is stable at 0.9 V.Simulation results show that the PSR of conventional capless-LDO circuit increases to a peak at the UGF of the loop and then begin to decrease through the capacitor-to-ground path at the output node. The highest PSR is even greater than 0 dB. The LDO using the new substrate ripple injection technology can adequately suppress the PSR peak and achieve the entire frequency band above -20 dB. Compared with the conventional structure, the PSR at the peak increases by more than 20 dB. The LDO can be applied to RF circuits that require low voltage power supplies.

A capacitor-less Low dropout regulator(LDO) with a low quiescent current and high transient response was designed through a SMIC 0.18 μm BCD process. The error amplifier adopts trans-conductance enhancement to achieve higher loop gain and unit gain bandwidth under low static current conditions. Owing to the use of high gain error amplifiers, the transient response can be enhanced by appropriately reducing the power transistor size. The secondary pole of the loop was increased using active feedback, without introducing additional static current.Simultaneously, when the output voltage of the LDO changed, the dynamic current of the power transistor gate could be increased, achieving a high transient response. In addition, through active feedback, a feedback resistor connected in parallel with a small capacitor was adopted to improve the loop stability. The software Cadence Spectre was used to simulate and verify the LDO circuit. The results show that the static current of LDO is 10 μA. When the load current is 1 mA, the maximum phase margin reaches 70.9°. When the LDO load current is switched from 1 to 100 mA with a switching time of 500 ns, the undershoot voltage is 134.7 mV, and the recovery time of the undershoot voltage is 1 μs. When the LDO load current is switched from 100 to 1 mA with a switching time of 500ns, the overshoot voltage is 155.5 mV, and the recovery time of the overshoot voltage is 430 ns.

A low-dropout linear regulator with high power supply rejection(PSR) and low quiescent current was designed using a 0.18 μm BCD process. A detailed analysis was conducted on the effects of multiple power ripple propagation paths on the PSR of the system. A three-stage error amplifier with a dual-rail power supply was designed to optimize the PSR at low-middle frequency. Additionally, a pre-regulator was introduced to reduce the influence of the voltage reference module on the low-frequency PSR of the system. An ultra-low quiescent currentvoltage reference based on the depletion transistor was designed to lower the quiescent current of the system.Simulation results demonstrate that the quiescent current can be as low as 5 μA at different output voltages, and within a load current range of 250 mA, the PSR is below -110 dB at 1 kHz and below -55 dB at 1 MHz

A behavioral model of a read-write control system for synchronous-pipelined static random access memory (SRAM) was designed. The control signals and working timing requirements of the SRAM chip were analyzed, and a behavioral model of a read-write system for the SRAM chip was built using Verilog hardware description language. The system consists of three components, the host, main controller, and memory chip, with the main controller further comprising two submodules, the signal source generator and data transceiver controller.The system behavioral model was simulated and verified using ModelSim software. The simulation results show that the system control model can read and write the SRAM chip correctly in non-burst (regular), linear burst, and interleaved burst operation modes. The number of source control signals from the host decreases to the minimum;thus, the read and write control procedure is considerably simplified. The data are sampled and transmitted with the double edges of the system clock, thus improving the stability of the system.

A four-level pulse amplitude modulation (PAM4) SerDes transmitter for high-speed inter-chip interconnections was designed using a 65 nm CMOS technology. The entire transmitter comprises most significant bit (MSB) channels, least significant bit (LSB) channels, clock generation paths, feedforward equalization modules, and interface drivers. A latchless parallel-to-serial conversion technique is used to minimize power consumption. A fractional feedforward equalization technique is employed to extend the frequency compensation range beyond the Nyquist frequency to enhance the adaptability of the output signal to the channel. Additionally, a 4∶1 parallel-to-serial converter with pre-charge ability is utilized to mitigate the impact of the charge-extraction effects. Simulation results demonstrate that the designed transmitter achieves a 56 Gbit/s PAM4 output signal at a supply voltage of 1 V, a clear output eye image, a high-linearity of the level mismatch ratio (RLM) of 93.1%, an output swing of 480 mV, and a power consumption of 75 mW.

With the trend of digitalization, intelligence, and integration in the industrial Internet of Things, the scale and complexity of physical quantities that control systems need to perceive are rapidly increasing. Among them, digital temperature sensors can directly convert temperature information into digital signals, with various advantages such as low cost, low area, low power consumption, small area and digital output. They can monitor system temperature data in real time and cooperate with feedback mechanisms for feedback adjustment. They have been widely used. Among various digital temperature sensors, the digital temperature sensor based on CMOS parasitic transistor (BJT) technology is easier to implement in the manufacturing process, and has high stability and precision, making it the preferred choice for industrial production. This article focuses on the implementation of temperature sensing digital temperature sensors based on BJT characteristics, summarizing their improvement routes, development status, and trends from both academic research achievements and industrial products,providing reference for subsequent temperature sensor research

During the post-Moore law period, one of the most effective means to delay the life of Moore’s law is achieving multifunctional, high-density, and miniaturized integration of functional and heterogeneous chiplets through advanced packaging technology. Among these blossoming solutions, embedding a silicon bridge chip into a substrate or interposer can solve the problem of local high-density signal interconnection between chiplets at a relatively lower cost than the through silicon via(TSV) interposer. Therefore, embedded bridge packaging is considered a compromise between the performance and cost of chiplets and heterogeneous integration in the industry. Several typically advanced packaging solutions based on bridge interconnection in the industry are summarized in this paper, and their process flow and technical difficulties are presented. Finally, the developmental direction of this type of advanced packaging technology is described.

Slurry is a crucial component of chemical mechanical polishing (CMP), with corrosion inhibitors being a fundamental part. Traditional corrosion inhibitors exhibit poor corrosion inhibition and low efficiency. However,compounded corrosion inhibitors have emerged as a focal point in CMP research owing to their high efficiency,superior corrosion inhibition effects, and environmental friendliness. In this study, the mechanism of azole corrosion inhibitors on Cu/Co barrier layers is analyzed, and a summary of the recent five-year research progress on new composite inhibitors in the CMP process globally is presented. Evaluations were conducted using various methods such as electrochemical techniques (EIS, OCP, and Tafel), surface analysis techniques (SEM and AFM), and molecular dynamics simulations (DFT and ReaxFF) to analyze the corrosion inhibition effect of these inhibitors.Finally, the current challenges and prospects of composite corrosion inhibitors are summarized

Thin-top silicon-on-insulator (SOI) lateral insulated-gate bipolar transistors (LIGBTs) have a high forward saturation voltage drop. When a shorted collector structure is introduced to reduce the trailing current of the turning-off state, the forward saturation voltage drop increases further. A novel fast-switching LIGBT (F-IELIGBT) device based on injection enhancement (IE) is proposed in this study, and its working mechanism is theoretically analyzed and verified through a simulation. The F-IE-LIGBT device is built on a thin-top SOI substrate, and its collector is designed using injection-enhanced and potential control structures. Combined simulation results show that the F-IE-LIGBT device can obtain a smaller forward saturation voltage drop, reduce the trailing current of the turning-off state, and achieve a fast turn-off characteristic. The F-IE-LIGBT device is highly suitable for SOI-based high-voltage power integrated circuits

Unlike the insulated gate structure of the Si-based metal-oxide-semiconductor field-effect transistors(MOSFETs), the gate of p-GaN-enhanced high electron mobility transistors (HEMTs) is a p-n junction, which is highly conductive under a large forward bias condition. The traditional method for the gate charge assumes that all current is injected and stored as gate charge. Thus, it is not applicable to p-GaN HEMT devices because the parameter values would be significantly overestimated. In this study, based on the basic accumulation process of the gate charge, we propose a dynamic capacitance method to extract the gate charge parameters of p-GaN E-HEMTs,which can reduce the impact of the forward leakage current. The capacitance method produces an ideal Miller plateau and characteristic curve, indicating significant potential for practical application.

An improved SiC Lateral bipolar junction transistor(LBJT) model considering the recombination current at the SiC/SiO2 interface in the base region is introduced. The difference between the lateral silicon carbide bipolar junction transistor and its vertical structure is analyzed. The epitaxial layer and the semi-insulating mechanism of the lateral BJT are equivalent to the substrate capacitance. An additional diode parallel to the base junction of the SiC BJT is introduced to describe the composite current. The behavior model of SiC LBJT is established based on the SGP model of a vertical SiC BJT. The base transit time of the LBJT model is calibrated,and the switching characteristics of the model are close to those of the actual device. On comparison with the measured data, the accuracy error between the output characteristic curve of the improved model is found to be smaller than that of the comparison with LBJT model data that does not consider the recombination current. This model can accurately describe the behavior of LBJT devices affected by the recombination current.

Using TCAD simulation to study the physical model and optimal structure of a two-dimensional tightly coupled resistance field plate current modulation principle.By optimizing key process and material parameters, the peak electric field in the drift region of the device was improved. Finally, under the same drift region doping, the breakdown voltage increased by 273% compared to the theoretical breakdown voltage of a one-dimensional PN junction. Under the same normalized breakdown voltage variation range of 10%, the allowable redundancy of charge variation in the drift region was expanded by 15 times compared to the existing traditional PN superjunction.Compared to symmetric resistive field-effect devices, asymmetric optimized resistive field-effect devices can better achieve structural miniaturization and high-density design under existing processes

A simulation analysis model of a 3D-packaging through glass via (TGV) was established. The highfrequency signal characteristics of TGV were analyzed, and the simulation results of the return loss (S11) were obtained. The influences of the signal frequency, type, maximum diameter, height, and minimum diameter of the TGV on the S11 were studied. The maximum diameter, height, and minimum diameter of the TGV were selected as the design parameters, and the S11 at 10 GHz was obtained as the target value. Seventeen groups of experimental simulation calculations were designed using the response surface method, and the relationship between the S11 of the TGV and its key structural parameters was fitted. The fitting model was optimized by combining a genetic algorithm, and the optimal combination parameters of the TGV S11 were obtained as follows: a maximum diameter of 65 μm, height of 360 μm, and minimum diameter of 44 μm. The optimal combination parameters were verified.The simulation results of the optimal combination parameters are 1.593 5 dB less than the S11 of the basic model,and the structure of the TGV is optimized.

To solve the application demand of silicon carbide diodes in high temperature (>200 ℃) and high voltage (>20 kV) environments, we fabricated a three-chamber shell using a ceramic processing technology of injection molding. Compared with traditional plastic sealing material, the ceramic shell significantly improves the working temperature and insulation voltage resistance characteristics of the device and can be used for hightemperature applications of silicon carbide materials. To solve the problem of shell cracking caused by material deformation after the temperature cycle test, we used ANSYS software to simulate the structural stress caused by temperature change and optimize the shell partition structure. The optimized shell structure passed the environmental stress test. With this structure, shells of different voltages can be developed with single-, double-,and multi-chamber structures. Similarly, shells with different forward rectification capabilities can be developed using different chamber sizes.

To address the problem of solder joint cracking in low-cost chip carrier (LCCC) packaging devices under temperature cycling loads, we first analyze the failure phenomenon and mechanism and establish a finite element model for simulating failure stress. Two stress relief schemes for the printed circuit board (PCB) are proposed to reduce the thermal stress caused by the mismatch in the coefficient of thermal expansion (CTE) between packaging materials. The impact of different hole sizes in the single-hole scheme and different hole quantities for the array-hole scheme on the thermal fatigue life were analyzed and studied. Subsequently, a novel stacked solder column stress buffering scheme is proposed to mitigate the impact on PCB layout density. Sensitivity analysis was performed for different stacked board thicknesses and solder column spacings. The results indicate that larger opening areas, thinner stack boards, and denser solder columns effectively reduce the solder joint stress,enhance the solder joint thermal fatigue life, and significantly improve the thermal fatigue reliability of LCCC packaging devices.

High-speed A/D converters are important components in equipment, and their working environment is deteriorating with the continuous increase in device conversion clock frequency. Accurately testing the time parameters is particularly essential for comprehensively evaluating the performance of A/D converters. Currently,the time parameters for high-speed A/D converters are primarily tested by directly testing the output through an oscilloscope with a high sampling speed. In this study, the time-domain reconstruction of high-speed A/D converters is proposed. It can be used to test the time parameters of high-speed A/D converters through computer digital signal processing and avoid dependence on the sampling speed of oscilloscopes. Moreover, by studying the time-domain reconstruction of high-speed A/D converters and its application, this study verifies the correctness of the principle through experiments.

Design and implement a ultra-high-speed data acquisition and analysis platform, consisting of FPGA data acquisition excitation boards, test analysis software, and PCs. This system is used for the testing and analysis of analog-to-digital converters (ADC) and digital-to-analog converters (DAC) using the JESD204C interface protocol. The platform is constructed from three aspects: component selection, PCB design and simulation,excitation, and software testing to ensure stable operation of the platform at the transmission rate of the JESD204C protocol. Based on this platform, dynamic performance tests were conducted on a 6 GSPS dual-channel 16 bit ADC and a 12 GSPS four-channel 16 bit DAC chip. The test results show that the SNR of the ADC is 56.3 dBFS, and the SFDR of the DAC is 65.5 dBFS, with performance indicators close to the manual values, indicating that the functionality and performance of the data acquisition platform have been verified and can be extended to testing other chips using the JESD204C interface protocol, demonstrating a certain degree of versatility.

Tampering with FPGA bitstreams and then running a cryptographic algorithm would result in ciphertext errors. This phenomenon can be used to theoretically analyze the secret key of a device. This analysis method often requires adversaries to fully understand the corresponding relationship between the internal structure of the target FPGA and the bitstream. However, reversing the bitstream is difficult and impractical. This study proposes an automatic fault injection analysis method against FPGA bitstreams. This method does not involve reversing engineering, and combined with the persistent fault analysis theory proposed by Zhang Fan et al., it considers the wrong output caused by tampering with algorithm constants, as an exploitable fault. An experiment on voltage fault injection by Spider on a Xilinx-7 series FPGA development board shows that the AES-128 bit key can be obtained within 480 wrong ciphertexts, and the data collection and analysis can be completed within 10 min.For easy encryption of the bitstream, the plaintext bitstream can be obtained using the electromagnetic side-channel analysis method. Subsequently, combined with the analysis method in this study, the AES key can be successfully broken.

Based on a 300-mm 0.18-μm MS 5-V process platform, a 1k×16 one-time programmable (OTP) device is designed and streamed, and the structure, working principle, and process of the storage unit that may affect the data retention life are analyzed. To model the retention characteristics of OTP devices, we conducted hightemperature aging experiments using different samples according to the Arrhenius life model, and data were collected after testing. Additionally, the maximum retention time of the sample data was calculated using linear fitting under conditions of 225, 250, and 275 ℃. Finally, under the worst product conditions that may occur in the production process, the activation energy and maximum data retention time of the floating gate charge leakage under different failure conditions were calculated through the mathematical fitting of 1/(kT ) and the data retention time curve.

This paper focuses on the design of RF filtering front-end module. In view of the RF signal transmission and isolation problems involved in the miniaturized and highly integrated design of the module, a refined three-dimensional electromagnetic field modeling simulation analysis is carried out to improve the model accuracy. In order to verify the simulation design accuracy, the key structural model are fabricated and deembedding tested.And an L-band miniaturized RF filtering front-end module has been fabricated. The module size is 14.97 mm×12.01 mm×1.29 mm. The number of the integrated filters is 16. The insertion loss is ≤5.2 dB, and the out-of-band rejection is ≥42.5 dB.