This paper presents a low-power, high-precision oversampling SAR ADC circuit fabricated using 65 nm CMOS technology. It analyzes the impact of DAC mismatch and comparator noise on ADC performance and employs a second-order CIFF passive integration and mismatch error shaping technique to significantly reduce in-band noise and harmonics, as well as mitigate the effect of CDAC capacitor array mismatch. Additionally, an analog three-level prediction scheme is proposed to address the dynamic range loss caused by MES. The SAR ADC circuit achieves an SNDR of 87.4 dB, a power consumption of 95 μW, and an FoM value of 183.8 dB at a 10 MS/s sampling clock and an oversampling ratio of 12.