The effective resolution of successive-approximation (SAR) analog-to-digital converters (ADCs) is primarily limited by sampling noise, analog-to-digital converter (DAC) mismatch, and comparator noise. This work presents a noise-shaping SAR ADC design that addresses all of these error sources. Sampling noise is mitigated using a kT/C noise cancellation technique combined with resampling. DAC mismatch is managed through data-weighted averaging (DWA) and mismatch error shaping (MES), while comparator noise is reduced using a second-order passive noise-shaping (NS) technique. Designed in a 40 nm CMOS process, the simulation results show that the ADC achieves an 86.8 dB signal-to-noise and distortion ratio (SNDR) across a 2.8 MHz bandwidth with a power consumption of 3.8 mW.