Microelectronics, Volume. 55, Issue 1, 134(2025)

An Interconnect Delay Prediction Model for ASIC Chips Based on LightGBM

CHEN Lin, TAO Runzhe, XIE Yuchi, FU Qiutao, and DI Zhixiong
Author Affiliations
  • School of Information Science and Technology, Southwest Jiaotong University, Chengdu 611756, P R China
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    As process node advances and integrated circuits scale up, interconnect delay increasingly dominates total delay. Traditional reliance on timing analysis tools for calculating interconnect delays during physical implementation hinders design completion speeds. We propose an interconnect delay prediction model based on LightGBM, aiming for both efficiency and accuracy. Unlike existing models that only focus on the parasitic parameters of interconnects, it also innovates by incorporating density features aware of routing resources and statistical global features that expand data dimensionality, employing the LightGBM model to achieve accurate predictions of interconnect delays. Compared to existing methods, our model significantly enhances prediction accuracy, reducing the overall mean absolute error to 0.452 ps—a 64.1% decrease in error. These findings confirm the effectiveness of the proposed method, providing a novel approach for interconnect delay prediction in physical design routing stage.

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    CHEN Lin, TAO Runzhe, XIE Yuchi, FU Qiutao, DI Zhixiong. An Interconnect Delay Prediction Model for ASIC Chips Based on LightGBM[J]. Microelectronics, 2025, 55(1): 134

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    Paper Information

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    Received: Mar. 11, 2024

    Accepted: Jun. 19, 2025

    Published Online: Jun. 19, 2025

    The Author Email:

    DOI:10.13911/j.cnki.1004-3365.240056

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