This paper presents a novel trench SiC power MOSFET device with an inherent self-biased PMOS for clamping the potential of the P-shield region at the bottom of the gate trench. The integrated PMOS has the P-shield region at the bottom of the trench serving as the source, the P+ source region as the drain, and the source metal filling the trench acting as the gate, with the gate and drain being short-circuited. By utilizing the clamping effect of this PMOS, the potential of the P-shield region at the bottom of the gate trench can be regulated. When the device is on, the PMOS is cut off, allowing the P-shield region to float, thereby improving the JFET effect in the channel region of the SiC MOSFET and reducing the specific on-resistance (R_{on, sp}) of the device. When the device is under high drain voltage, the self-biased PMOS turns on, clamping the potential of the P-shield region, thus enhancing the electric field shielding effect of the P-shield region on the gate oxide layer and improving the reliability of the device. Simulation results show that the proposed device has a breakdown voltage (BV) of 1 430 V and a R_{on, sp} of 1.70 mΩ‧cm², exhibiting comparable BV and improved R_{on, sp} compared to conventional devices. The gate-drain charge and high-frequency figure of merit are enhanced by more than 14.3% and 20%, respectively. Additionally, the proposed device has a lower gate oxide E-field than conventional devices.