With the rapid development of communication industry, especially mobile communication, the low-end frequency of radio spectrum has become saturated. Using various modulation methods or multiple access technologies to expand the capacity of communication system and improve the utilization of spectrum can not meet the needs of future communication development. Therefore, the realization of high-speed and broadband wireless communication is bound to develop new spectrum resources to microwave high-frequency band. Millimeter wave can effectively solve many problems faced by high-speed broadband wireless access because of its short wavelength and wide frequency band, so it has a wide application prospect in short-range wireless communication. Various semiconductor devices are the hardware basis of information and communication technology (ICT). Creative research and development of emerging semiconductor technologies and circuits to meet the application of millimeter wave wireless communication is the main technical driver to improve the capacity of communication system and solve the key problems of building a new generation of communication system. Along the innovation and development of millimeter wave semiconductor device technology, this paper analyzed and summarized the development trend of millimeter wave system and device technology of the fifth and sixth generation mobile communication technologies (5G and 6G) from the system architecture, semiconductor materials and technology, device design and packaging test of key technologies such as phased array. Taking the MADAS program of DARPA as an example, this paper explained the research frontier and progress of military millimeter wave device technology.

With the development of applications such as the Internet of Things and mobile devices, the demand for image sensors, which is important for information perception, continues to grow. The analog-to-digital converter (ADC) is an important part of the image sensor, which is responsible for converting the detected analog signal into a digital signal. It not only increases the anti-interference ability and improves the performance of the system, but also enables data processing within the chip and improves the system integration. In order to adapt to the development trend of image sensors towards large arrays, high frame rates, low power consumption, and small pixel sizes, ADCs face challenges in terms of speed, power consumption, and area. Several main architectures of ADCs used in image sensors were reviewed in this paper, and the advantages and disadvantages of these architectures were analyzed. Research progress and future development directions were summarized.

With the development of integrated circuit process, the sizes of transistors are reducing, and the ADCs become faster with lower power consumption. On the other hand, smaller size brings more mismatch error, which will affect the accuracy, so it is necessary to introduce error calibration. In this paper, firstly, the typical error sources and traditional calibration methods of ADC were analyzed. Secondly, basic principle of neural network was given together with the most popular researches for ADC calibration based on neural network, and the advantages and disadvantages of different methods were analyzed. Finally, a system level simulation based on neural network was proposed to calibrate a 14-bit pipelined ADC. The results showed that ENOB was improved from 10 bit to 125 bit, and SFDR was improved from 80 dB to 100 dB.

The radiation effect has become a major issue affecting the reliable application of integrated circuits in space. The research progress of radiation resistant reinforcement technology was reviews in this article. Firstly, the radiation resistant reinforcement technology was introduced. Then, the foreign research development and current situation of radiation resistant reinforcement technology were reviewed, and the management approach, technical route, results and progress of the United States in radiation resistant reinforcement technology were introduced. Finally, the progress of the domestic radiation resistant reinforcement technology was introduced. It pointed out that the study of the development of radiation resistant reinforcement technology in the United States could promote the development of radiation resistant reinforcement technology in China. This review had certain significance for the practical application and promotion of anti-irradiation reinforcement technology.

A high speed pipelined ADC using low threshold technology was implemented in a 0.35 μm standard CMOS process. The ADC included sample and hold circuits, a pipelined ADC core, clock circuits and reference circuits. Compared with traditional circuits, the amplifier of sample and hold circuit had adopted low threshold technology, and the advantage was that it used a low threshold device to compensate the amplifier based on a specific process. So a high gain bandwidth was achieved, and the speed of ADC had increased. Simultaneously, a new protection circuit was designed to effectively ensure the normal operation. An unique design technology in bias circuit could not only optimize the gain and bandwidth of the transconductance amplifier, but also adjust the working status of the MOS device. The architecture of the converter with a realized 14-bit resolution from analog to digital signal was 10 stage pipelined structure that consisted of 4 bit+8×15 bit+3 bit. Under the conditions of 5 V supply and 100 MHz clock, the simulation results showed that SINAD was 74.76 dB, and SFDR was 87.63 dBc. The chip area was 50 mm×50 mm.

A switching sequence optimization technique for current steering DAC was proposed. Firstly, the MSB current source array was divided into four parts and located in the four quadrants. In each quadrant, the switching sequence optimization technology was used to eliminate the second-order amplitude error caused by the PVT change of the current source array. Secondly, the current source array with optimized switching sequence in the quadrant was sorted and reorganized according to amplitude changes to form the final current source and switching sequence, eliminating first order amplitude error and other residual errors. Compared with conventional switching sequence optimization techniques, this technique could more effectively reduce the amplitude error and improve the static performance of the DAC. To verify the proposed switching sequence optimization technique, a 12-bit 200 MS/s current steering DAC was implemented in a 40 nm CMOS process. The test results showed that through proposed switching sequence optimization technique, the INL and DNL of the DAC were reduced from 0.63 LSB and 0.37 LSB to 0.54 LSB and 0.25 LSB, respectively.

A timing optimization technique was studied based on 10 bit pipelined ADC. The technique prolonged the phase holding time of MDAC. Without increasing power consumption and chip area, the effective numbers of bit (ENOB) was increased from 93 bit to 98 bit under 20 MS/s sampling rate of a 10 bit pipelined ADC, and the accuracy was improved by 5%. The maximum sampling rate of the ADC was increased from 21 MS/s to 29 MS/s with ENOB no less than 93 bit, and the speed was increased by 35%. The higher the sampling rate of ADC, the more significant the improvement effect was. This technique was especially suitable for high-speed and high-precision pipelined ADC, and also provided ideas for high-speed and high-precision design optimization of ADC.

A discrete-time Σ- A/D converter was presented. The A/D converter was based on the cascade noise shaping (MASH) structure design. The whole converter was composed of programmable gain amplifier, cascade modulator and digital decimation filter. The A/D converter was implemented in a standard 018 μm CMOS technology, and the chip area was 6 mm2. Test results showed that the A/D converter had an SNR of 106 dB, an SFDR of 110 dB, a power consumption of only 20 mW at 16 kS/s output data rate.

An analog-storage based analog-to-digital converter (ADC) was designed for the applications of pulsed light detection and ranging (LiDAR), where a high speed sequence control logic circuit and an analog-storage array were designed, combined with a low speed pipelined ADC and an accompanied phase-locked-loop (PLL) circuit. The simulation results showed that the proposed analog-storage based ADC could achieve an equivalent performance of 16 GHz ADC by a low speed 25 MHz ADC in the actual applications of LiDAR.

A low power Σ- analog-to-digital converter with a third-order feed-forward 1 bit architecture was designed. In order to reduce power consumption, the OTA of the switched capacitor integrator used a floating inverter amplifier, which had the advantages of low power consumption, dynamic operation, fully differential circuit structure and stable common mode point without the need for CMFB. Fabricated in a SMIC 180 nm CMOS process, the prototype modulator achieved 919 dB signal-to-noise-and-distortion ratio (SNDR), 93 dB signal-to-noise ratio (SNR), 101 dB dynamic range (DR), and 15 bit effective number of bit (ENOB) over a 20 kHz signal bandwidth with 4 MHz sampling frequency. The circuit consumed only 78 μW at a 1.2 V supply.

A high energy efficiency phase quantization A/D converter (PH ADC) based on successive approximation of load redistribution was designed. Aiming at the problem of low conversion accuracy caused by poor linearity of quantization level in traditional structure, the linearity of comparison level was improved by establishing phase mapping relationship and adopting linear regression curve technology. At the same time, the number of comparison levels was reduced to half of the traditional structure, which reduced the capacitor array area, power consumption and complexity of the circuit. Furthermore, a low power monotonic switching mode and a common-mode voltage lifting circuit were introduced to raise the weighted comparison level to the supply voltage, avoiding the design of additional reference level generating circuits. The circuit simulation results based on 55 nm CMOS process showed that the ENOB was more than 56 bit and the FOM value was 2438 fJ/conv under the whole process corner condition.

A bandpass Σ- ADC with a continuous/discrete time hybrid structure for IF-digitizing was designed. The modulator adopted a sixth-order bandpass multi-bit quantization structure, and the loop filters of the modulator included two continuous time resonators followed by a discrete time resonator. The use of capacitor based digital calibration technology enabled the accurate calibration of resonance frequencies of the LC resonator and RC resonator to be fclk/8 precisely. The quantizer was realized by a 3 bit flash ADC. At the same time, DWA algorithm was used to calibrate the mismatch between feedback DAC units. The overall IF-digitizing receiver was fabricated in a 018 μm SiGe BiCMOS process. The post-simulation results showed that the Σ- ADC consumed 21 mW under a 33 V power supply voltage. With a fclk of 18 MHz and an OSR of 45, a SNR of 89 dB and a SFDR of 95 dB could be obtained within the 200 kHz signal bandwidth.

To solve the timing mismatch between time-interleaved ADC channels, a calibration algorithm based on delay filtering was proposed. This algorithm was a pure off-chip calibration algorithm. The delay deviation of each sub-channel was extracted by off-chip FFT analysis and refiting the ideal signal, then it calculated the corresponding FIR filter coefficient to compensate the delay deviation. The calibration algorithm solved the problem of insufficient precision of TI ADC caused by timing mismatch between sub-channels. The algorithm was applied to a 12 GS/s 12 bit ADC interleaving board. The results show that the mean increase of SFDR and ENOB was 31.356 4 dBc and 3.177 6 bit respectively.

A passive noise shaping SAR ADC circuit was designed in a 65 nm CMOS process. On the basis of SAR ADC, only 6 switches and 2 capacitors were added to the circuit to realize noise shaping, and the whole circuit structure was simple, which could effectively improve the accuracy of SAR ADC. In addition, a passive gain of 2 was achieved, and the noise suppression effect of the comparator was enhanced. The whole loop constructed the noise transfer function with good noise suppression effect, and eliminated the use of residual sampling module and multipath comparator. The simulation results showed that the designed 10-bit noise shaping SAR ADC circuit could reach 124 effective bits and the power consumption was 459 μW under the condition of 33.3 MHz sampling rate, 2.08 MHz bandwidth and 1.2 V input voltage.

A novel sampling distortion cancellation circuit utilizing dual-plate sampling for high-precision differential SAR ADCs was proposed. To eliminate the signal distortion caused by the sampling switch’s on-resistance, the sampling circuit consisted of two paths, whose components’ size were proportional to the other, and the error charges of two ends of the differential were cancelled by subtraction between the two paths. Compared with traditional top-plate sampling or bottom-plate sampling, the dual-plate sampling amplified the amplitude of differential input, avoiding the attenuation of the input caused by the subtracting. Simulation results showed that the THD of the proposed sampling distortion cancellation circuit was reduced by 15 dB and the SFDR was increased by 19 dB at 1 MS/s sampling rate and 300 kHz sinusoidal input signal. The SNR of the sampling circuit was 112 dB.

A background calibration algorithm based on pruning neural network was introduced, which could simultaneously calibrate multiple non-ideal factors such as capacitance mismatch, offset and gain of high-precision single-channel SAR ADC, and effectively improved the accuracy of SAR ADC. This algorithm could not only achieve the full connected neural network calibration effect, but also eliminate the weights with small contributions, which reduced the resource consumption of the calibration circuit and speeded up the neural network calibration algorithm. The simulation results showed that when the signal frequency was close to the Nyquist frequency, the 16 bit 5 MS/s SAR ADC was calibrated, and after calibration, the effective number of bits of the ADC was increased from 74 bit to 156 bit, and the spurious free dynamic range was increased from 46.8 dB to 126.2 dB.

A high linearity and ultra-bandwidth sample/hold circuit with bridge shunt-series cascade structure. The sample/hold circuit included three units, such as input buffer, auxiliary switch and SEF switch. The improved auxiliary switch module unit with bridge shunt -series cascade structure greatly improved the linearity and bandwidth of the circuit. The sample/hold circuit was designed in a 0.13 μm SiGe bipolar process, and it was powered by -4.75 V and 2 V dual supply voltage. The simulation results showed that SFDR was 69.60 dB, THD was -65.25 dB, and -3 dB bandwidth was 35.43 GHz under the conditions of 100 fF sampling capacitance, 6.25 GHz sampling frequency and 10.28 GHz input frequency.

A high speed and low power binary-search ADC was designed in a 65 nm CMOS technology. Compared with the traditional binary-search architecture, the employed comparator was composed of a two-stage dynamic preamplifier and a one-stage dynamic latch, which reduced the static current and achieved extremely low power consumption. The offset voltage was reduced to a level that do not cause decision error, and the external digital calibration module was omitted. As a result, the chip area was reduced, and calibration accessories were avoided to slow down the comparator. The post-simulation results showed that the effective bit of the binary-search ADC reached 4.59 bit, and the power consumption was only 1.57 mW at 1 GHz sampling frequency.

A radiation hardened low power pipelined 8 bit ADC was designed and implemented. The optimal inter-stage resolution and pipelined structure were determined by analyzing the effect of the pipelined structure resolution. A variety of circuit structures were adopted to reduce the circuit power consumption. In order to achieve the radiation hardened goal, the circuit was designed with radiation hardened techniques. The test results showed that the ADC had a SFDR of 596 dBc, a total steady-state dose capacity of 2 500 Gy(Si), a single-particle latch threshold of 75 MeV·cm2/mg, and a power consumption of 69 mW at 3 V power supply voltage, 100 MHz clock input frequency, and 701 MHz analog input frequency. The ADC was fabricated in a 035 μm CMOS process. Its area was 075 mm2. This ADC was suitable for communication systems in space environments.

A high speed and high precision folding and interpolating A/D converter based on 013 μm SiGe BiCMOS process was proposed. A new sampling/holding circuit based on SEF switch was adopted to fix the voltage in the holding stage, thus realizing signal sampling with high speed, high precision and high linearity. The folding amplifier with emitter follower was adopted to form a four-level cascade structure of average folding and annular interpolation, which reduced the number of comparators, the settling time and the overall power consumption. A new two-stage comparator was used to isolate analog and digital signals and optimize kickback noise. The use of small size transistors reduced the regeneration time. Under 3.3/5 V power supply and 0.13 μm SiGe BiCMOS process, the folding and interpolating A/D converter achieved a sampling rate of 1.6 GS/s, a SFDR of 71.3 dB, a SNDR of 63.6 dB and a ENOB of 10.27 bit.

In order to solve the impact of capacitance mismatch on accuracy in high-precision SAR ADC, a second-order error-feedback mismatch error shaping (EFMES) SAR ADC with 16-bit accuracy, 500 kS/s sampling rate and 33 V working voltage was designed. Second order EFMES structure and dynamic element matching technology were adopted to reduce the influence of capacitor mispairing on ADC accuracy. The EFMES SAR ADC was designed in a SMIC 018 μm CMOS process. When the input signal amplitude was 2.6 V and the sampling rate was 500 kS/s, the power consumption of the ADC was 8382 mW, the SNDR was 93.67 dB, the ENOB was 15.27 bit, and the SNDR-based FoM was 168.4 dB.

A continuous time level crossing analog-to-digital converter (LCADC) for ECG signal processing was designed. The circuit eliminated the DAC module of traditional voltage mode and adopted N-bit current-steering DAC to solve the problem of capacitor leakage of traditional voltage mode DAC. The circuit included a voltage to current converter, a 7-bitcurrent-steering DAC, a level crossing detection module and an offset calibration compensatim module. This circuit was designed in a SMIC 0.18 μm CMOS process, and the supply voltage was 1 V. The simulation results showed that the total power consumption was 8.1 μW @500 Hz. The data were processed through MATLAB. The signal-to-noise distortion ratio (SNDR) was 53.8 dB @500 Hz, and ENOB reached 8.64 bit. The SNDR range within the input signal range was 52.8~63.6 dB, and the circuit power consumption range was 7.3~8.5 μW. Therefore, the circuit was suitable for the acquisition of low frequency ECG signals.

A high precision and low power digital temperature sensor was presented. An internal parasitic PNP was used to sense the temperature. A 14-bit high precision Σ- ADC was designed to convert the voltage signal, which was generated by the front temperature sensing module, into the digital signal. Then the signal was normalized in digital domain at the final output. Compared with the temperature sensors adopting a traditional SAR ADC core, the proposed digital temperature sensor achieved lower power consumption. This circuit was designed and implemented in a 0.18 μm CMOS technology. The measurement results indicated that the temperature accuracy was ±0.7 ℃(at -55 ℃~125 ℃), and the chip area was 1.2 mm2.

The theory of injecting dither signal was analyzed to improve the performance of ADC. An appropriate dither signal was selected to inject into the ideal quantized model. The simulation demonstrated that the dither injecting technique could randomize the periodic triangular distribution of quantization error. In the practical application of the dither injecting technique, firstly, the dither injecting simulation was completed based on 10 bit 25 MS/s pipelined ADC model, and the SFDR of ADC was improved from 7469 dB to 85 dB. Then, the dither injecting test was carried out for two kinds of ADC chips. The SFDR of ADC chips were increased by 829 dB and 597 dB respectively depending on dither injecting technique. The experiment gave a conclusion that the dither injection technique could significantly improve SFDR of ADC, made a full preparation for the integration of noise circuit module into ADC.

A single event effect test system for analog-to-digital converter (ADC) with static inputs was proposed. The system was built on NI’s Peripheral Component Interconnection Extensions for Instrumentation platform (PXI). By applying trigger mode, the different instrument modules in PXI platform could cooperate and respond in high frequency. By applying continuous data capture and real-time comparison with expected value, the system could observe and store outputs beyond ADC’s error-band window. Based on this system, a single event effect radiation experiment was carried out upon a self-developed 10 bit 25 MS/s ADC. The result showed that the system could precisely capture sensitive data, which provide comprehensive data services for single event effect measurement and radiation-hardened design of ADC.

The measurement techniques of high speed ADC were studied. A measurement scheme based on high speed ADC AD9433 was proposed. The principles of two kinds of analog input driving circuits were described systematically. Two analysis methods of analog driving circuit and clock circuit jitter were introduced in detail, The above theoretical analysis was applied to AD9433 measurement scheme. The measurement results proved the correctness of the above theoretical analysis.