Microelectronics
Co-Editors-in-Chief
Xiaojun Fu
2022
Volume: 52 Issue 2
26 Article(s)
WANG Tao, and LAI Fan

With the rapid development of communication industry, especially mobile communication, the low-end frequency of radio spectrum has become saturated. Using various modulation methods or multiple access technologies to expand the ca

Jan. 16, 2023
  • Vol. 52 Issue 2 169 (2022)
  • YU Shanzhe... ZHOU Ye, ZHUO Yi, ZHANG Yacong, LU Wengao and CHEN Zhongjian|Show fewer author(s)

    With the development of applications such as the Internet of Things and mobile devices, the demand for image sensors, which is important for information perception, continues to grow. The analog-to-digital converter (ADC) is an im

    Jan. 16, 2023
  • Vol. 52 Issue 2 181 (2022)
  • LI Jiashen... LI Long, DENG Honghui, CHEN Hongmei, MENG Xu and YIN Yongsheng|Show fewer author(s)

    With the development of integrated circuit process, the sizes of transistors are reducing, and the ADCs become faster with lower power consumption. On the other hand, smaller size brings more mismatch error, which will affect the

    Jan. 16, 2023
  • Vol. 52 Issue 2 191 (2022)
  • MAO Haiyan... LAI Fan, XIE Jiazhi and ZHANG Jian|Show fewer author(s)

    The radiation effect has become a major issue affecting the reliable application of integrated circuits in space. The research progress of radiation resistant reinforcement technology was reviews in this article. Firstly, the radi

    Jan. 16, 2023
  • Vol. 52 Issue 2 197 (2022)
  • ZENG Tao... GUO Liang, HOU Jiang, LIAO Wang, CHEN Xue, WANG Guoqiang and HUANG Xiaozong|Show fewer author(s)

    A high speed pipelined ADC using low threshold technology was implemented in a 0.35 μm standard CMOS process. The ADC included sample and hold circuits, a pipelined ADC core, clock circuits and reference circuits. Compared with tr

    Jan. 16, 2023
  • Vol. 52 Issue 2 206 (2022)
  • YUAN Yidan... LIN Guowei, MA Juncheng and WU Kejun|Show fewer author(s)

    A switching sequence optimization technique for current steering DAC was proposed. Firstly, the MSB current source array was divided into four parts and located in the four quadrants. In each quadrant, the switching sequence optim

    Jan. 16, 2023
  • Vol. 52 Issue 2 211 (2022)
  • [in Chinese]... [in Chinese], [in Chinese], [in Chinese], [in Chinese], [in Chinese], [in Chinese], [in Chinese], [in Chinese] and [in Chinese]|Show fewer author(s)

    A timing optimization technique was studied based on 10 bit pipelined ADC. The technique prolonged the phase holding time of MDAC. Without increasing power consumption and chip area, the effective numbers of bit (ENOB) was increas

    Jan. 16, 2023
  • Vol. 52 Issue 2 217 (2022)
  • SHEN Xiaofeng... LI Liang, FU Dongbing, WANG Youhua and ZHU Can|Show fewer author(s)

    A discrete-time Σ- A/D converter was presented. The A/D converter was based on the cascade noise shaping (MASH) structure design. The whole converter was composed of programmable gain amplifier, cascade modulator and digital decim

    Jan. 16, 2023
  • Vol. 52 Issue 2 223 (2022)
  • ZENG Qingcheng... GUO Jianping and CHEN Dihu|Show fewer author(s)

    An analog-storage based analog-to-digital converter (ADC) was designed for the applications of pulsed light detection and ranging (LiDAR), where a high speed sequence control logic circuit and an analog-storage array were designed

    Jan. 16, 2023
  • Vol. 52 Issue 2 229 (2022)
  • LIN Hongkai, and CHEN Qunchao

    A low power Σ- analog-to-digital converter with a third-order feed-forward 1 bit architecture was designed. In order to reduce power consumption, the OTA of the switched capacitor integrator used a floating inverter amplifier, whi

    Jan. 16, 2023
  • Vol. 52 Issue 2 236 (2022)
  • CHEN Hongmei... WANG Xuerui, WAN Fangli and YIN Yongsheng|Show fewer author(s)

    A high energy efficiency phase quantization A/D converter (PH ADC) based on successive approximation of load redistribution was designed. Aiming at the problem of low conversion accuracy caused by poor linearity of quantization le

    Jan. 16, 2023
  • Vol. 52 Issue 2 240 (2022)
  • ZHANG Qinfeng... FENG Kai, SHI Chunqi, ZHANG Runxi and YE Mingyuan|Show fewer author(s)

    A bandpass Σ- ADC with a continuous/discrete time hybrid structure for IF-digitizing was designed. The modulator adopted a sixth-order bandpass multi-bit quantization structure, and the loop filters of the modulator included two c

    Jan. 16, 2023
  • Vol. 52 Issue 2 246 (2022)
  • LI Rui... TANG He, WU Jin, GUO Xuan, ZHOU Lei, JI Eryou and PENG Xizhu|Show fewer author(s)

    To solve the timing mismatch between time-interleaved ADC channels, a calibration algorithm based on delay filtering was proposed. This algorithm was a pure off-chip calibration algorithm. The delay deviation of each sub-channel w

    Jan. 16, 2023
  • Vol. 52 Issue 2 253 (2022)
  • YIN Yongsheng... LEI Lei, FAN Xuelian and DENG Honghui|Show fewer author(s)

    A passive noise shaping SAR ADC circuit was designed in a 65 nm CMOS process. On the basis of SAR ADC, only 6 switches and 2 capacitors were added to the circuit to realize noise shaping, and the whole circuit structure was simple

    Jan. 16, 2023
  • Vol. 52 Issue 2 260 (2022)
  • CHEN Shangcun... DENG Honghui, CHEN Chaochao and YIN Yongsheng|Show fewer author(s)

    A novel sampling distortion cancellation circuit utilizing dual-plate sampling for high-precision differential SAR ADCs was proposed. To eliminate the signal distortion caused by the sampling switch’s on-resistance, the sampling c

    Jan. 16, 2023
  • Vol. 52 Issue 2 265 (2022)
  • WANG Liang... DENG Honghui, CHEN Hao and YIN Yongsheng|Show fewer author(s)

    A background calibration algorithm based on pruning neural network was introduced, which could simultaneously calibrate multiple non-ideal factors such as capacitance mismatch, offset and gain of high-precision single-channel SAR

    Jan. 16, 2023
  • Vol. 52 Issue 2 270 (2022)
  • LIANG Hongyu... WANG Yan and LI Ruzhang|Show fewer author(s)

    A high linearity and ultra-bandwidth sample/hold circuit with bridge shunt-series cascade structure. The sample/hold circuit included three units, such as input buffer, auxiliary switch and SEF switch. The improved auxiliary switc

    Jan. 16, 2023
  • Vol. 52 Issue 2 283 (2022)
  • CHIO U-Fat... XIONG Deyu, WANG Wei, ZHANG Dingdong, ZHANG Shan, YUAN Jun, YANG Zhenglin and LI Junfeng|Show fewer author(s)

    A high speed and low power binary-search ADC was designed in a 65 nm CMOS technology. Compared with the traditional binary-search architecture, the employed comparator was composed of a two-stage dynamic preamplifier and a one-sta

    Jan. 16, 2023
  • Vol. 52 Issue 2 289 (2022)
  • ZHOU Xiaodan... LIU Tao, FU Dongbing, LI Qiang, LIU Jie and GUO Gang|Show fewer author(s)

    A radiation hardened low power pipelined 8 bit ADC was designed and implemented. The optimal inter-stage resolution and pipelined structure were determined by analyzing the effect of the pipelined structure resolution. A variety o

    Jan. 16, 2023
  • Vol. 52 Issue 2 295 (2022)
  • ZOU Peizhe... WANG Yonglu and YI Zhou|Show fewer author(s)

    A high speed and high precision folding and interpolating A/D converter based on 013 μm SiGe BiCMOS process was proposed. A new sampling/holding circuit based on SEF switch was adopted to fix the voltage in the holding stage, thu

    Jan. 16, 2023
  • Vol. 52 Issue 2 301 (2022)
  • SHI Yuda, and CHEN Qunchao

    In order to solve the impact of capacitance mismatch on accuracy in high-precision SAR ADC, a second-order error-feedback mismatch error shaping (EFMES) SAR ADC with 16-bit accuracy, 500 kS/s sampling rate and 33 V working voltag

    Jan. 16, 2023
  • Vol. 52 Issue 2 306 (2022)
  • WEI Rongshan... LIN Cheng and CHEN Qunchao|Show fewer author(s)

    A continuous time level crossing analog-to-digital converter (LCADC) for ECG signal processing was designed. The circuit eliminated the DAC module of traditional voltage mode and adopted N-bit current-steering DAC to solve the pro

    Jan. 16, 2023
  • Vol. 52 Issue 2 312 (2022)
  • LIAO Wang... HOU Jiang, GUO Liang, SU Hao, CHEN Xianghong and HUANG Xiaozong|Show fewer author(s)

    A high precision and low power digital temperature sensor was presented. An internal parasitic PNP was used to sense the temperature. A 14-bit high precision Σ- ADC was designed to convert the voltage signal, which was generated b

    Jan. 16, 2023
  • Vol. 52 Issue 2 318 (2022)
  • ZHU Beili... QI Feitao, ZHANG Lin, LIU Tao, LIU Hainan, TENG Rui, LI Bo, ZHAO Fazhan, LUO Jiajun and HAN Zhengsheng|Show fewer author(s)

    The theory of injecting dither signal was analyzed to improve the performance of ADC. An appropriate dither signal was selected to inject into the ideal quantized model. The simulation demonstrated that the dither injecting techni

    Jan. 16, 2023
  • Vol. 52 Issue 2 323 (2022)
  • LIU Tao... QI Feitao, ZHU Beili, ZHANG Lin, LIU Hainan, TENG Rui, LI Bo, ZHAO Fazhan, LUO Jiajun and HAN Zhengsheng|Show fewer author(s)

    A single event effect test system for analog-to-digital converter (ADC) with static inputs was proposed. The system was built on NI’s Peripheral Component Interconnection Extensions for Instrumentation platform (PXI). By applying

    Jan. 16, 2023
  • Vol. 52 Issue 2 329 (2022)
  • ZHANG Lin... QI Feitao, LIU Tao, ZHU Beili, LIU Hainan, TENG Rui, LI Bo, ZHAO Fazhan, LUO Jiajun and HAN Zhengsheng|Show fewer author(s)

    The measurement techniques of high speed ADC were studied. A measurement scheme based on high speed ADC AD9433 was proposed. The principles of two kinds of analog input driving circuits were described systematically. Two analysis

    Jan. 16, 2023
  • Vol. 52 Issue 2 334 (2022)
  • Please enter the answer below before you can view the full text.
    Submit