With the rapid development of communication industry, especially mobile communication, the low-end frequency of radio spectrum has become saturated. Using various modulation methods or multiple access technologies to expand the ca
With the development of applications such as the Internet of Things and mobile devices, the demand for image sensors, which is important for information perception, continues to grow. The analog-to-digital converter (ADC) is an im
With the development of integrated circuit process, the sizes of transistors are reducing, and the ADCs become faster with lower power consumption. On the other hand, smaller size brings more mismatch error, which will affect the
The radiation effect has become a major issue affecting the reliable application of integrated circuits in space. The research progress of radiation resistant reinforcement technology was reviews in this article. Firstly, the radi
A high speed pipelined ADC using low threshold technology was implemented in a 0.35 μm standard CMOS process. The ADC included sample and hold circuits, a pipelined ADC core, clock circuits and reference circuits. Compared with tr
A switching sequence optimization technique for current steering DAC was proposed. Firstly, the MSB current source array was divided into four parts and located in the four quadrants. In each quadrant, the switching sequence optim
A timing optimization technique was studied based on 10 bit pipelined ADC. The technique prolonged the phase holding time of MDAC. Without increasing power consumption and chip area, the effective numbers of bit (ENOB) was increas
A discrete-time Σ- A/D converter was presented. The A/D converter was based on the cascade noise shaping (MASH) structure design. The whole converter was composed of programmable gain amplifier, cascade modulator and digital decim
An analog-storage based analog-to-digital converter (ADC) was designed for the applications of pulsed light detection and ranging (LiDAR), where a high speed sequence control logic circuit and an analog-storage array were designed
A low power Σ- analog-to-digital converter with a third-order feed-forward 1 bit architecture was designed. In order to reduce power consumption, the OTA of the switched capacitor integrator used a floating inverter amplifier, whi
A high energy efficiency phase quantization A/D converter (PH ADC) based on successive approximation of load redistribution was designed. Aiming at the problem of low conversion accuracy caused by poor linearity of quantization le
A bandpass Σ- ADC with a continuous/discrete time hybrid structure for IF-digitizing was designed. The modulator adopted a sixth-order bandpass multi-bit quantization structure, and the loop filters of the modulator included two c
To solve the timing mismatch between time-interleaved ADC channels, a calibration algorithm based on delay filtering was proposed. This algorithm was a pure off-chip calibration algorithm. The delay deviation of each sub-channel w
A passive noise shaping SAR ADC circuit was designed in a 65 nm CMOS process. On the basis of SAR ADC, only 6 switches and 2 capacitors were added to the circuit to realize noise shaping, and the whole circuit structure was simple
A novel sampling distortion cancellation circuit utilizing dual-plate sampling for high-precision differential SAR ADCs was proposed. To eliminate the signal distortion caused by the sampling switch’s on-resistance, the sampling c
A background calibration algorithm based on pruning neural network was introduced, which could simultaneously calibrate multiple non-ideal factors such as capacitance mismatch, offset and gain of high-precision single-channel SAR
A high linearity and ultra-bandwidth sample/hold circuit with bridge shunt-series cascade structure. The sample/hold circuit included three units, such as input buffer, auxiliary switch and SEF switch. The improved auxiliary switc
A high speed and low power binary-search ADC was designed in a 65 nm CMOS technology. Compared with the traditional binary-search architecture, the employed comparator was composed of a two-stage dynamic preamplifier and a one-sta
A radiation hardened low power pipelined 8 bit ADC was designed and implemented. The optimal inter-stage resolution and pipelined structure were determined by analyzing the effect of the pipelined structure resolution. A variety o
A high speed and high precision folding and interpolating A/D converter based on 013 μm SiGe BiCMOS process was proposed. A new sampling/holding circuit based on SEF switch was adopted to fix the voltage in the holding stage, thu
In order to solve the impact of capacitance mismatch on accuracy in high-precision SAR ADC, a second-order error-feedback mismatch error shaping (EFMES) SAR ADC with 16-bit accuracy, 500 kS/s sampling rate and 33 V working voltag
A continuous time level crossing analog-to-digital converter (LCADC) for ECG signal processing was designed. The circuit eliminated the DAC module of traditional voltage mode and adopted N-bit current-steering DAC to solve the pro
A high precision and low power digital temperature sensor was presented. An internal parasitic PNP was used to sense the temperature. A 14-bit high precision Σ- ADC was designed to convert the voltage signal, which was generated b
The theory of injecting dither signal was analyzed to improve the performance of ADC. An appropriate dither signal was selected to inject into the ideal quantized model. The simulation demonstrated that the dither injecting techni
A single event effect test system for analog-to-digital converter (ADC) with static inputs was proposed. The system was built on NI’s Peripheral Component Interconnection Extensions for Instrumentation platform (PXI). By applying
The measurement techniques of high speed ADC were studied. A measurement scheme based on high speed ADC AD9433 was proposed. The principles of two kinds of analog input driving circuits were described systematically. Two analysis