A bandpass Σ- ADC with a continuous/discrete time hybrid structure for IF-digitizing was designed. The modulator adopted a sixth-order bandpass multi-bit quantization structure, and the loop filters of the modulator included two continuous time resonators followed by a discrete time resonator. The use of capacitor based digital calibration technology enabled the accurate calibration of resonance frequencies of the LC resonator and RC resonator to be fclk/8 precisely. The quantizer was realized by a 3 bit flash ADC. At the same time, DWA algorithm was used to calibrate the mismatch between feedback DAC units. The overall IF-digitizing receiver was fabricated in a 018 μm SiGe BiCMOS process. The post-simulation results showed that the Σ- ADC consumed 21 mW under a 33 V power supply voltage. With a fclk of 18 MHz and an OSR of 45, a SNR of 89 dB and a SFDR of 95 dB could be obtained within the 200 kHz signal bandwidth.