A continuous time level crossing analog-to-digital converter (LCADC) for ECG signal processing was designed. The circuit eliminated the DAC module of traditional voltage mode and adopted N-bit current-steering DAC to solve the problem of capacitor leakage of traditional voltage mode DAC. The circuit included a voltage to current converter, a 7-bitcurrent-steering DAC, a level crossing detection module and an offset calibration compensatim module. This circuit was designed in a SMIC 0.18 μm CMOS process, and the supply voltage was 1 V. The simulation results showed that the total power consumption was 8.1 μW @500 Hz. The data were processed through MATLAB. The signal-to-noise distortion ratio (SNDR) was 53.8 dB @500 Hz, and ENOB reached 8.64 bit. The SNDR range within the input signal range was 52.8~63.6 dB, and the circuit power consumption range was 7.3~8.5 μW. Therefore, the circuit was suitable for the acquisition of low frequency ECG signals.