A high-efficiency buck converter circuit was designed in a 0.35 μm BCD process, with 10 V~24 V input voltage, 5 V~12 V output voltage, and 100 mA load current. A simple circuit structure based on the hysteresis control was presented. And the fewer power consumption of the buck converter was achieved by using the sleep mode. In the active mode, the quiescent current was about 110 μA, and in the sleep mode, the quiescent current was about 11 μA. For the phenomenon that the switching loss accounted for a larger proportion under light load conditions, a floating gate voltage circuit for the synchronous power MOSFET MN was designed to reduce the switching loss. Simulation results showed that with 10 V input and 5 V output, the efficiency could reach 67.7% under 0.1 mA load, and the efficiency was higher than 91% above 10 mA load.
Large integer multiplication is the most time-consuming operation during encrypted data calculation. It is particularly important to improve large integer multiplier speed in machine learning based on fully homomorphic encryption. A design scheme of high speed 768 kbit large integer multiplier was proposed in this paper. The critical component 64k-point finite field number theory transform (NTT) was decomposed into 16-point NTT. And through dichotomy processing, the pipeline architecture of 16-point NTT was refined. To increase the speed of the multiplier, addition and shift were adopted to achieve the modular-subtraction unit, and data interaction was accomplished by using an efficient non-conflict address algorithm. The multiplier was deployed on the Altera Stratix-V FPGA development board. And the experimental results showed that the circuit had a working frequency of 169.23 MHz and took 0.317 ms to complete the large integer multiplication. Comparing with the state-of-the-art works, our speed performance was improved by 1.2 times to 7.3 times.
A low-voltage low-power CMOS ring oscillator with pseudo-differential structure was designed in the TSMC 28 nm CMOS process, which included oscillator’s bias circuit, ring oscillator and output buffer. The pseudo-differential ring oscillator utilized a five-stage delay unit with a Maneatis symmetrical load to improve the VCO’s tuning linearity and tuning range. Pre-simulation on Cadence Spectre showed that when the VCO was operating at 0.9 V supply voltage, the frequency tuning range was 0.65 GHz to 4.12 GHz. The tuning linearity was excellent in the most area of tuning range. With a center frequency of about 2.3 GHz, the phase noise was -79.06 dBc/Hz@1 MHz. The output buffer stage enabled the rail-to-rail output swing and the duty ratio of 50%. The power consumption of the ring oscillator was approximately 5.7 mW.
A synapse circuit with low power consumption, high energy efficiency and compact structure was designed in a 65 nm CMOS technology. It could be used in Spike Neuron Network (SNN) system. A switched capacitor circuit structure was used in the synapse circuit to receive directly the pulse signal from the neuron circuit. The weight of synapse could be adjusted by Spike Timing Dependent Plasticity (STDP) learning rule, and the tunable asymmetric of the weight learning window was realized, so that the synaptic circuit could adapt to different applications. The simulation results showed that the synaptic circuit consumed around 0.4 pJ/spike.
A high frequency voltage controlled active inductor (HFVCAI) with multiple reconfigurable performances was proposed, which was mainly composed of a first gyration loop, a second gyration loop and a tuning branch circuit. And the first gyration loop was in parallel with the second gyration loop, and the tuning branch circuit was connected to the first gyration loop. Furthermore, both gyration loops were equipped with external tuning terminals. Therefore, taking full advantage of combinational adjustment of the three external tuning terminals, three reconfigurable performances of the HFVCAI could be achieved as follows: had a wide tuning range of the inductance and simultaneously kept a large and constant Q value in the high frequency operation region; had almost unchanged Q peak values and inductances at different frequencies; had a wide range of adjustment of the operation frequency bandwidth without the change in the peak value of inductance. The results showed that in the high frequency region of 5.10~6.60 GHz, the tuning range of inductance was greater than 27 nH, and the Q value could remain greater than 10. At the high frequencies of 4.72 GHz, 5.10 GHz and 5.46 GHz, the Q peak values could be high up to 1 063, 1 053, 1 033 respectively with the variation of only 2.8%, meanwhile, the inductances were 202 nH, 198 nH and 191 nH with the variation of only 5.4%. The operation frequency bandwidth could be adjusted from 6.02 GHz to 7.67 GHz with the large variation of 27.4%, while the peak value of inductance was varied from 404 nH to 395 nH with the variation of only 2.2%.
Since the parallel-circuit class-E power amplifier (PA) has the advantages of simple structure and high efficiency, it has been widely used in many applications. To solve the problem of narrow bandwidth and low efficiency of the parallel-circuit class-E PA, an improved technology for its output matching network was proposed in this paper. A hybrid π-type structure was used as the output matching network of the PA, which not only performed the conversion between the best impedance and the standard impedance within a wide working bandwidth, but also effectively suppressed the second harmonic component, in turn to improve the circuit’s efficiency. In order to verify the validity of the proposed theory, based on a 0.25 μm GaN HEMT process, a monolithic-integrated class-E power amplifier with simple structure, high efficiency and high power was designed in this paper. The post-layout simulation results showed that the output power was greater than 40 dBm, and the power-added efficiency was 51.8% to 63.1% in the 2.5～3.7 GHz operating frequency range. The size of layout was 2.4 mm×2.9 mm.
The influence of the nonlinearity of polysilicon silicon resistance on the overall circuit performance of signal chain was introduced, and the causes of the nonlinearity of polycrystalline silicon resistance were analyzed. Two nonlinear compensation design methods, substrate potential compensation and composite polysilicon compensation, were proposed. The performance of 12 bit D/A converter without compensation and with the new compensation method were compared by simulation and test. The results showed that the D/A converter with polycrystalline silicon resistance compensation and nonlinear compensation achieved better linearity.
By using a clever circuit structure and analog signal processing method, a circuit was designed to extract weak pulse signal from clutter. Firstly, the input signal was saturated and amplified, and then filtered in two stages. The output signal of the primary filter was compared with the output signal of the secondary filter in the comparator, so as to generate the pulse signal, and the output pulse width was adjustable. The structure of the circuit was simple and the use of fewer components was convenient for miniaturization. The circuit was processed by thick film technology. The results showed that the pulse width error of the circuit was 1.0% and the output pulse delay time was 51 ns. The circuit had the characteristics of strong ability to detect weak signal, small change of pulse width, strong anti-interference, small size, low power consumption and good consistency, and it was suitable for mass production.
Based on the traditional asynchronous FIFO circuits, a controllable delay asynchronous FIFO circuit structure was designed. The delay control module was added to the circuit while realizing the data transmission across clock domain. The integral delay was controlled by adjusting the difference between the read pointer and the write pointer, and the fractional delay was controlled by adjusting the phase difference between the read clock and the write clock. The VCS verification platform was established for functional verification. The results showed that data transmission across clock domain and delay dynamic control could be achieved in this FIFO circuit. The output skew caused by data source misalignment could be compensated when multichips worked at the same time. Based on a 180 nm standard CMOS process library, the read clock frequency was 389 MHz, and the write clock frequency was 778 MHz. The logic resource area was 41 071 μm2.
In non-volatile compute-in-memory (CIM) chips, the gate equivalent capacitance of large-scale array and the equivalent capacitance of long-distance transmission line severely restricted the switching speed of word line drive circuit (WLDC). The different voltage of multi-voltage range required by the nonvolatile CIM device was much larger than the withstand voltage of single transistor in the WLDC. Therefore, this paper proposed a high speed WLDC for CIM. By combining with the working principle of array, a multi-stage pre-processing voltage control method was adopted to transmit a variety of high voltages in multiple voltage domains in a selective hierarchical manner, which could greatly reduce the propagation delay. In addition, a clamp voltage divider structure was adopted to reduce the voltage drop of single device in the WLDC, which could solve the voltage withstand and high voltage switching problems of the WLDC. Simulation results showed that the circuit could convert the 1.2 V input of 100 MHz frequency into the high voltage output. The range of a single high speed WLDC output voltage could reach -10 V to 10 V, and the intrinsic delay was 1.4 ns. When the load was 5 pF, the transmission delay was 8.9 ns.
A 56 Gbit/s PAM4 optical receiver front-end was designed in a 65 nm CMOS process. A transimpedance amplifier (TIA) used a common-gate feedforward structure to reduce the input impedance, and an inductor was added at the input port to improve the bandwidth and sensitivity at the input of TIA. A multi-stage variable gain amplifier (VGA) with linear gain control was adopted to adjust the output swing automatically at the post stage. The output buffer (OB) employed the source degeneration technique so as to expand the bandwidth. The post-simulation results showed that the -3 dB bandwidth was 24.4 GHz, the maximum gain reached 66 dBΩ, and the input-referred noise current was 17.0 pA·Hz-1/2 with 100 fF photodiode capacitance. Under different process corners and input currents, the output eye-diagrams had small jitter and fine opening degree. The average power consumption was 42.5 mW at different process corners from a voltage supply of 1.2 V.
To solve the problem of poor output power and matching performance of traditional frequency triplier, a triplier was proposed while a filter was used as matching circuit based on TSMC 0.18μm CMOS process. This triplier had good matching performance and low power loss, and the output power of the third harmonic was improved. The static characteristics of the transistor were analyzed to further improve the output power. The measured results after the flow showed that the maximum output power was -6.2 dBm when the input power was 0 dBm, the fundamental wave suppression ratio was greater than 12.35 dBc, and the second harmonic suppression ratio was greater than 8.2 dBc within range of 31.5~36 GHz output frequency. The DC power consumption was 36.9 mW at 1.8 V power supply. The core circuit area was 0.35 mm2.
Physical Unclonable Function (PUF), as a circuit structure that can effectively deal with hardware security issues, has received extensive attention in recent years. Among them, the Ring Oscillator (RO) PUF does not require a completely symmetrical wiring method, so it is considered to be one of the most ideal PUF structures. However, the existing RO PUF design is more complicated and requires "hard macros" to fix the circuit, which results in poor portability of PUF. A RO PUF was implemented by using the inherent carry logic resources in FPGA in this paper. By cascading 11 XOR gates in 3 carry logics, the 11th-order oscillation ring was configured to solve the problem of portability and to avoid the use of "hard macros" to fix the circuit. The proposed structure was tested by using Xilinx Spartan-6. Experimental results showed that the proposed RO PUF achieved an uniformity of 50.65%, an uniqueness of 48.48% and a bit error rate of 1.56%. At the same time, this design had the characteristics of easy implementation, single resource occupation, and no manual layout.
Graphene has unique properties such as high electron mobility, large specific surface area, high mechanical strength, excellent chemical and thermal stability, and high electrical conductivity at room temperature. It is one of the most popular two-dimensional materials today. Compared with traditional inorganic oxide materials, graphene gas sensors have the advantages of low operating temperature, low energy consumption, and high recovery. The research progresses of two graphene gas sensors were summarized in this paper. Firstly, according to the different gas selectivity, graphene gas sensors were divided into CO and CO2 gas sensors. Then, the sensitivity, gas response sensitivity and response time were analyzed and compared, respectively, which had certain guiding significance for the practical application and promotion of this type of sensor.
Due to the high breakdown voltage characteristics of the laterally diffused metal oxide semiconductor (LDMOS), this device is a protection device that prevents electrostatic discharge (ESD) in high-voltage applications. In the traditional structure, the robustness of LDMOS is relatively poor, which is caused by the inherent uneven conduction characteristics of the device itself and the Kirk effect. The silicon-controlled rectifier (SCR) can be embedded in the LDMOS structure to become the NPN_LDMOS structure. However, the inherent positive feedback effect of the SCR will cause its holding voltage to be lower and increase the risk of latch-up. A new type of device based on NPN_LDMOS was proposed, which could achieve a higher holding voltage and a small area. Based on TCAD simulation, the simulation TLP experimental results showed that the holding voltage of the device was increased from 7.3 V to 22.5 V, and the chip area was not increased, which proved that this structure had excellent immune latch-up capabilities.
In order to study the amplification effect of multi-layer graphene on surface acoustic waves, the variable conductivity of graphene carriers was analyzed under an external electric field, and the amplification performance of multi-layer graphene surface acoustic wave amplifiers was studied under different substrates. The graphene surface acoustic wave amplifiers with ZnO and CdS substrates were compared and studied, and their magnifications under different carrier drift speeds were studied respectively. The results showed that, with ZnO as the substrate, when the carrier drift velocity was larger than and close to the surface acoustic wave phase velocity, the amplification performance was the best, and α could reach 34.92 dB.
The electrostatic discharge (ESD) protection requirements of integrated circuits with operating voltage of 5 V can be met by the trigger voltage of the low-voltage triggering silicon controlled rectifier (LVTSCR), but the LVTSCR’s low holding voltage always lead to severe latch-up. In order to solve the problems of latch-up, the improved LVTSCR was proposed. An N-type heavily doped buried layer was inserted below the N type well, which changed the current flow path after LVTSCR triggered and reduced the accumulation of holes in the substrate. Thereby the Webster effect of the LVTSCR was inhibited and the holding voltage was increased. Sentaurus TCAD simulation results showed that the holding voltage of the proposed device was increased from 2.44 V to 5.57 V without increasing the additional area, which could avoid the latch-up effect of the integrated circuit with the working voltage of 5 V.
In order to solve the conflict between high trigger voltage and low holding voltage in the traditional SCRs used for high voltage BCD process, a novel latch-up immunity multi-embedded-well SCR (MEWSCR) ESD device was proposed. Compared with the traditional SCR structure, firstly, MEWSCR device inserted an auxiliary discharge device by moving N+ and P+ diffusion region of the anode and cathode. The auxiliary device induced the secondary trigger effect and increased the holding voltage. Secondly, N-type and P-type shallow wells were embedded under the P+ diffusion region of the anode and N+ diffusion region of the cathode, respectively. The embedded shallow well enhanced the SRH recombination of non-equilibrium carriers to reduce the snapback effect of SCR, which improved the holding current. Based on a 0.18 μm BCD process, TCAD software was used to simulate. The results showed that the holding voltage of the new MEWSCR device increased to 23 V, and the holding current increased to more than 1 A, which met the requirements of ESD design window.
To solve the problems of poor out-of-band suppression ability and uneven in-band group delay of RF MEMS filters, an L-band RF MEMS linear phase filter with narrow bandwidth, low insertion loss and high selectivity was designed. Narrow-band transmission was realized by selecting substrate material with high dielectric constant, and linear phase was realized by using resonator with double-layer inter-digital structure. The volume of the circuit was reduced. The HFSS software was used to optimize the performance of the filter. The results showed that the center frequency of the filter was 1.46 GHz, the in-band insertion loss was less than 1.97 dB, the in-band group delay fluctuation was less than 2 ns, and the out-of-band rejection was more than 70 dB at 1 GHz around the center frequency. The overall circuit size was 10 mm×7.2 mm×0.62 mm.
A two-stage protection SCR (TSPSCR) was proposed to reduce the trigger voltage. The P-ESD layer was implanted in the traditional LVTSCR, and an additional diode was added. Because of the higher doping concentration of P-ESD layer, the device could trigger the first-stage discharge path by avalanche breakdown earlier, thus opening the second-stage discharge path. The Sentaurus TCAD simulation results showed that compared with conventional SCRs, the device had a lower trigger voltage from 10.59 V to 4.12 V, a maintenance voltage of 1.25 V, and a leakage current of 7.85 nA at 1 V DC voltage. The optimized TSPSCR could be used in advanced circuits with 1 V operating voltage.
Compared with traditional VDMOS, the superjunction and high k dielectric structure VDMOS could achieve higher breakdown voltage and lower on-resistance. The effects of various structural parameters on electric field distribution, breakdown voltage and specific on-resistance of 3D cylindrical high k VDMOS with and without interfacial charges were systematically summarized by simulation software. The variation trend and reason of breakdown voltage and specific on-resistance with parameters were studied and qualitatively analyzed. This study provided a reference for the design of high k VDMOS.
Based on through-silicon via (TSV) technology, a spiral inductor for 3D integrated circuits was proposed. In the practical application, the electric field, temperature field and force field of the TSV inductor were coupled with each other, which would eventually degrade the actual electrical performance. Considering the effects of P- and N-type substrates, the effects of multi-physics coupling on TSV-based 3D spiral inductor were researched using COMSOL software. The results showed that the impact of multi-physical field coupling was much significant in P-type silicon substrate, and the variations of the inductance and quality factor reached as much as 14.13% and 5.91%, respectively.
Traditional low-voltage triggered silicon controlled rectifier(LVTSCR)has low holding voltage, which may lead to latch-up risk when applied to ESD protection on chip. In this paper, an embedded shunt path LVTSCR was proposed. Based on a 0.18 μm CMOS technology, Sentaurus-TCAD software was used to simulate the human body model, and the quasi-static characteristics of the device were analyzed. The results showed that the novel device could effectively improve the holding voltage while maintaining the trigger voltage and ESD protection. By optimizing the key dimension D6, the device’s holding voltage was increased to more than 5.5 V, which could be safely applied to 5 V operating voltage circui,t and the latch-up effects were avoided.
A p-SiC/n-GaN heterojunction double drift (DDR) IMPATT diode was fabricated while p-GaN was replaced by wide bandgap p-SiC. The output characteristics of AC large signal were simulated numerically. The results showed that compared with the traditional GaN single drift (SDR) IMAPTT diode, the breakdown voltage, optimal negative conductance, AC power density and DC-AC conversion efficiency of the new p-SiC/N-GaN DDR device were significantly improved, and the device had a wider oscillation frequency band. The new structure of the device had significant application potential in AC power density, which reached 1.97 MW/cm2. The diode was based on the wide gap semiconductor material, which provided reference value for the design and manufacture of GaN and SiC IMPATT device.
In order to obtain higher threshold voltage, a novel AlGaN/GaN high electron mobility transistor (HEMT) enhanced by double heterojunction under gate was proposed. The basic mechanism was analyzed by using the double heterojunction charge control model, and the threshold voltage expression was derived. The simulation results showed that the threshold voltage of the device was linear with the Al content of the modulation layer. When the Al content of the modulation layer was less than the barrier layer, the threshold voltage increased, otherwise it decreased, and the thickness of the modulation layer would increase this modulation effect. When the modulation layer Al content was 0% and the thickness was 112 nm, the device had a threshold voltage of 2.13 V and a specific on-resistance of 1.66 mΩ·cm2. Compared with the conventional fluted gate structure, the threshold voltage of the new structure was increased by 173%.
The failure behaviors of memory chips under ESD and electromagnetic interference (EMI) have been characterized by many researches, whereas the frequency response characteristics of continuous wave immunity of SRAM has not been researched yet. The failure behavior and mechanism of SRAM under RF EMI (RFI) was studied in this paper. The SRAM chips RFI testing results revealed that SRAM failure behavior was related to its operating state. Transistor-level simulation was carried out by Hspice. Results showed that the SRAM was highly immune to interference within data hold and weakly immune to interference within read/write state. Further study on the failure mechanism revealed that power-side disturbances caused drift and jitter in the path delay, resulting in SRAM read and write failure. This study could provide guidance for the reliability design of memory or system on chip.
In the field of microelectronic packaging where the integration and power consumption of chips are increasing, the FBGA package has a larger storage capacity with the same volume. Based on the finite element and orthogonal method, the reliability performance of FBGA solder joints under thermal cycling load was analyzed, and a optimization design with more robust solder joint structural parameters was carried out. The results showed that the solder joint array had an important influence on the thermal reliability of the FBGA structure. The optimized combination scheme was the 12*12 solder joint array, where the radial size of the solder joint was 0.42 mm, the height was 0.38 mm, and the pitch was 0.6 mm. After optimization verification, the optimization scheme reduced the equivalent plastic strain range by 89.92% compared with the original design scheme, and the signal-to-noise ratio was increased to 17.72 dB, having achieved the purpose for optimizing the solder joint parameters.
For the need of radiation reliability analysis on the memory devices which were applied in the nuclear facilities, the threshold dose of the floating gate cells in a domestic NOR-type flash memory had been investigated. A reliability analysis method with extremely small sample size had been established by utilizing the SMOTE-Bootstrap algorithm. The experimental results showed that the dominant failure mode of the floating gate cell was the threshold voltage reduction due to charge loss in the floating gate, and the average verification error dose was 631.89±103.64)Gy(Si). The statistical analysis results showed that the radiation damage dose of the device obeyed the lognormal distribution. The SMOTE-Bootstrap algorithm avoided the problem that the conventional bootstrap method would cause an abnormal data concentration in the generated samples. Meanwhile, the algorithm had been proved to be suitable for the application of reliability analysis with extremely small sample size.