A discrete-time Σ- A/D converter was presented. The A/D converter was based on the cascade noise shaping (MASH) structure design. The whole converter was composed of programmable gain amplifier, cascade modulator and digital decimation filter. The A/D converter was implemented in a standard 018 μm CMOS technology, and the chip area was 6 mm2. Test results showed that the A/D converter had an SNR of 106 dB, an SFDR of 110 dB, a power consumption of only 20 mW at 16 kS/s output data rate.