A radiation hardened low power pipelined 8 bit ADC was designed and implemented. The optimal inter-stage resolution and pipelined structure were determined by analyzing the effect of the pipelined structure resolution. A variety of circuit structures were adopted to reduce the circuit power consumption. In order to achieve the radiation hardened goal, the circuit was designed with radiation hardened techniques. The test results showed that the ADC had a SFDR of 596 dBc, a total steady-state dose capacity of 2 500 Gy(Si), a single-particle latch threshold of 75 MeV·cm2/mg, and a power consumption of 69 mW at 3 V power supply voltage, 100 MHz clock input frequency, and 701 MHz analog input frequency. The ADC was fabricated in a 035 μm CMOS process. Its area was 075 mm2. This ADC was suitable for communication systems in space environments.