A low power Σ- analog-to-digital converter with a third-order feed-forward 1 bit architecture was designed. In order to reduce power consumption, the OTA of the switched capacitor integrator used a floating inverter amplifier, which had the advantages of low power consumption, dynamic operation, fully differential circuit structure and stable common mode point without the need for CMFB. Fabricated in a SMIC 180 nm CMOS process, the prototype modulator achieved 919 dB signal-to-noise-and-distortion ratio (SNDR), 93 dB signal-to-noise ratio (SNR), 101 dB dynamic range (DR), and 15 bit effective number of bit (ENOB) over a 20 kHz signal bandwidth with 4 MHz sampling frequency. The circuit consumed only 78 μW at a 1.2 V supply.