A high speed pipelined ADC using low threshold technology was implemented in a 0.35 μm standard CMOS process. The ADC included sample and hold circuits, a pipelined ADC core, clock circuits and reference circuits. Compared with traditional circuits, the amplifier of sample and hold circuit had adopted low threshold technology, and the advantage was that it used a low threshold device to compensate the amplifier based on a specific process. So a high gain bandwidth was achieved, and the speed of ADC had increased. Simultaneously, a new protection circuit was designed to effectively ensure the normal operation. An unique design technology in bias circuit could not only optimize the gain and bandwidth of the transconductance amplifier, but also adjust the working status of the MOS device. The architecture of the converter with a realized 14-bit resolution from analog to digital signal was 10 stage pipelined structure that consisted of 4 bit+8×15 bit+3 bit. Under the conditions of 5 V supply and 100 MHz clock, the simulation results showed that SINAD was 74.76 dB, and SFDR was 87.63 dBc. The chip area was 50 mm×50 mm.