A switching sequence optimization technique for current steering DAC was proposed. Firstly, the MSB current source array was divided into four parts and located in the four quadrants. In each quadrant, the switching sequence optimization technology was used to eliminate the second-order amplitude error caused by the PVT change of the current source array. Secondly, the current source array with optimized switching sequence in the quadrant was sorted and reorganized according to amplitude changes to form the final current source and switching sequence, eliminating first order amplitude error and other residual errors. Compared with conventional switching sequence optimization techniques, this technique could more effectively reduce the amplitude error and improve the static performance of the DAC. To verify the proposed switching sequence optimization technique, a 12-bit 200 MS/s current steering DAC was implemented in a 40 nm CMOS process. The test results showed that through proposed switching sequence optimization technique, the INL and DNL of the DAC were reduced from 0.63 LSB and 0.37 LSB to 0.54 LSB and 0.25 LSB, respectively.