A timing optimization technique was studied based on 10 bit pipelined ADC. The technique prolonged the phase holding time of MDAC. Without increasing power consumption and chip area, the effective numbers of bit (ENOB) was increased from 93 bit to 98 bit under 20 MS/s sampling rate of a 10 bit pipelined ADC, and the accuracy was improved by 5%. The maximum sampling rate of the ADC was increased from 21 MS/s to 29 MS/s with ENOB no less than 93 bit, and the speed was increased by 35%. The higher the sampling rate of ADC, the more significant the improvement effect was. This technique was especially suitable for high-speed and high-precision pipelined ADC, and also provided ideas for high-speed and high-precision design optimization of ADC.