The physical world we live in is analog. The role of analog electronics in modern information and communication technology (ICT) and computing systems includes such aspects as physical world sensing and interaction, computing, control, data conversion, communication, power supply, and measurement. Analog microelectronics devices, mainly analog integrated circuits , are key components in almost all digital-centric systems today, and are critical to the future development of information technology. In order to achieve the infrastructure construction goals of the information society, such as the new generation of ICT, industry 40, and the internet of things represented by the 5G and 6G communications, the primary and necessary condition is a fundamental breakthrough through analog hardware to achieve intelligent sensing, cognition, and processing of the physical world and machine interaction. This requires analog electronics technology to conduct research in wireless signal chain integrated circuits, computing paradigms and architectures, high-precision perception and control, as well as design, process and packaging test technologies for analog microelectronics, and meeting application-specific requirements, addressing such areas as computing paradigm and architecture innovations, compressed sensing, process technologies required for new architecture innovations, and the challenges posed by the development of high-band integrated circuits such as millimeter wave and terahertz. This paper discussed recent research advances at the frontiers of analog microelectronics and application technologies in terms of wireless signal chain integrated circuits, analog technologies in edge machine learning, high-precision sensing and control, and important process innovations, showing the key future trends in analog electronics.

In the past few years, the rising electromagnetic spectrum for wireless communications has been driven by the differences in the propagation characteristics of different bands, the demand for bandwidth, and the improved ability to utilize technology. In the field of communications, millimeter wave (mmW) low and medium frequency bands have been successfully engineered and started to be commercially deployed to meet the explosive growth in demand for wireless data transmission, especially for 5G communications. The optical communication for higher frequency electromagnetic waves with light waves as the carrier has also been maturely developed and applied for decades. Between conventional radio waves (millimeter waves) and conventional optics (far infrared), there exists a long-unused free spectrum resource, which is now collectively referred to as the terahertz (THz) band (01~10 THz). Due to the obvious advantages of the terahertz band in the field of high speed wireless communication, terahertz communication technology has the potential to become the core technology of 6G communication. It is foreseeable that the use of this technology will help 6G communication to realize the vision of full network coverage, high intelligence, and overall improvement of network security. This paper focused on the communication field, highly lighting the characteristics of the terahertz band, the types of devices, and process integration implementation technologies for building terahertz system functions. Finally, this paper predicted some application scenarios of terahertz communication technology, and then showed the contribution of this technology to the communication field and people's daily life.

A fully integrated low noise amplifier (LNA) for Wi-Fi 6 (5 GHz) was designed and implemented in a 55 nm standard CMOS process. The design included a source-degenerate cascode amplifier, a balun and a gain switching cell. All inductors were realized on chip. A balun was adopted as the load to perform the single-to-differential conversion. In addition, in order to deal with different input power, the LNA had high gain and low gain mode. Measurement results indicated that the LNA achieved a maximum voltage gain of 202 dB when switched to high gain mode, and the corresponding minimum noise figure was 2.2 dB. In low gain mode, the gain was 15 dB, and the corresponding maximum input -1 dB compression point was -3.2 dBm. The chip occupies a core area of 0.28 mm2, and the static power consumption was 10.2 mW.

A bias-circuit-noise cancellation VCO was designed and fabricated in a 0.18 μm CMOS process. By inserting a strobe circuit between the bias circuit and the VCO core, the noise voltage from the bias circuit could be low-pass filtered. Analyses showed that the corner frequency of the low-pass filter was dependent on the turn-on resistance and turn-off resistance of the strobe circuit as well as the duty cycle of the switching clock. Measurement results showed that with the assistance of the strobe circuit, the near-end phase noise of the VCO was reduced by 20 dB approximately, exhibiting a significant suppression for flicker noise from the bias circuit.

A CPW-fed planar wide-slot antenna was designed. The Koch fractal technology was used to broaden the bandwidth of the antenna, and the HFSS software was used to optimize the size and position of the CPW feeder and the rectangular matching stub. The return loss, the pattern and the gain of this wide slot antenna was measured. The measured result showed that the bandwidth of the antenna reached 14~5.8 GHz, and the in-band gain fluctuation was less than 3dB. The research of this antenna system had strong expansibility and application prospects in power detection, 5G communication, radar system, etc.

Based on the model of DC-DC converter transformer parasitic parameters, the finite element simulation analysis method was used to calculate the parasitic parameters of transformer. Combined with the circuit simulation analysis method, by studying different transformer winding strategies, the influence of different winding strategies on transformer parasitic parameters, voltage stress and noise of circuit was analyzed.

A 16-channel high speed front end readout circuit for CdZnTe detectors was designed in a 035 μm CMOS process. The circuit was composed of 16 analog channels, bias module and logic control module. Each channel included a charge-sensitive amplifier, a leakage current compensation circuit, a shaper circuit, a baseline hold circuit, a peak detection hold circuit and a time discriminator. The performance of the main circuit modules and the readout timing of the channel were analyzed at high incident frequency. The simulation results showed that the input energy range of the readout circuit was 29~430 keV@1~15 fC, the power consumption of each channel was less than 18 mW, the equivalent noise charge was 87.6e-, and the maximum compensation leakage current was 50 nA. The peak time was 150 ns, the channel gain was 50 mV/fC, the nonlinearity was less than 1%, and the maximum injection frequency was 500 kHz.

To solve the problem of poor transient response of capacitive-less low dropout linear regulators (LDO), a capacitive-less LDO circuit with transient load change sensing was designed in a 40 nm CMOS process. Active feedforward frequency compensation was used to achieve circuit stability. The transient detection circuit sensed the load changes, and provided a charge or discharge path for the gate of the power transistor to weaken the output voltage fluctuation. The simulation results showed that the maximum overshoot and undershoot voltage of the LDO were 100 mV and 140 mV respectively, and the stable time was 1 μs when the load current changed from 0 to 100 mA. The transient performance was greatly improved within the full load current range.

With the development of information security and communication technology, random number has been widely used in security chip, secure communication and other fields. In order to make the implementation of random number online detection method more quickly, this design optimized and derived the Chi-square test formula, which was convenient for hardware implementation. For each random number detection length of 128 bit, 256 bit and 512 bit, the more complex part of Chi-square test formula was removed by derivation, and the formula which was convenient for hardware implementation was obtained, so the formula was easy to be optimized and implemented by hardware. The correctness of the design was verified by VCS and Verdi simulation. Finally, the design was synthesized by using UMC55 technology library with Design Compiler tool. The area of 128 bit Chi-square module was 1 411 GE (number of equivalent NAND gates), which achieved a significant optimization effect while occupied a smaller area. Compared with the software implementation, the speed of 512 bit Chi-square module was increased by 50.08%, achieving higher random number online detection speed. It could be applied to hardware implementation scenarios with small area and high speed.

Based on a 018 μm CMOS process, a two-stage ultra-wideband low noise amplifier (LNA) was designed for the applications in wireless communication bands below 10 GHz. The first stage, based on the complementary common-source stage, introduced the structures of resistor feedback, inductance peaking technology and pseudo-resistor to improve the bandwidth and gain while reducing noise. The second stage introduced inductance peaking technology, gain auxiliary stage and buffer stage on the basis of common-source amplification, which were mainly used to increase the circuit gain and improve the output broadband matching characteristics. The simulation results showed that the gain was 14.2±0.2 dB, the noise figure (NF) was less than 3.97 dB, and the overall power consumption was 12.9 mW within the frequency range of 0.5~9.2 GHz.

According to the conversion relationship between fractional-order memory elements, a general equivalent circuit of fractional-order memory elements was designed. Without changing the topological structure of circuit, the equivalent circuit could convert any grounding fractional-order memory element into any floating fractional-order memory element by selecting the types of five impedance elements. In the simulation experiment, three kinds of fractional-order memory elements were realized respectively according to the proposed general equivalent circuit, and the characteristics of three kinds of fractional-order memory element were analyzed. The correctness of the equivalent circuit was verified.

Based on a 0.13 μm CMOS process, a new common-mode feedback circuit for three-stage fully differential operational amplifier was proposed and designed. A typical two-stage fully differential and source-follower structure with a Miller compensation structure was used as the amplification stage of the three-stage operational amplifier. By introducing a feedforward path in the common-mode feedback circuit to generate two zeros, the stability of the operational amplifier had been improved, which could solve the problem that multiple poles are difficult to compensate in the traditional common mode feedback loop. The simulation results showed that the gain was 70.4 dB, the unity gain bandwidth (GBW) was 56 MHz, and the phase margin was 85.5° under 1.2 V voltage. Compared with the traditional circuit without a feedforward path, the GBW and phase margin of the new common-mode feedback circuit were increased by 8.2 MHz and 17.4° respectively. An operational amplifier with this common-mode feedback structure could achieve lower power supply voltage and better phase margin.

A high frequency, high speed, low offset voltage dynamic comparator, which was composed of an improved pre-differential operational amplifier and a differential latch was proposed. The differential pre-amplifier employed a cross-coupling load structure of paired PMOS transistors to increase the common-mode gain as well as to reduce the input offset voltage. The output-stage latch module used a dual-tail current source to suppress common-mode noise, so as to improve the output offset and speedup the signal comparison. A clock-controlled switching transistor was designed to replace the traditional reset control module, so as to optimize the layout area, while constructing a positive feedback loop to further accelerate the circuit resetting and settling of output comparison signal. A 65 nm/12 V standard CMOS process was adopted to implement the circuit design of the proposed dynamic comparator, and the features in terms of delay, offset voltage and power consumption were analyzed and evaluated based on process corner and Monte Carlo simulation by Cadence Spectre tool. The results showed that the average power consumption was 117.1 μW at 12 V power supply voltage and 1 GHz input sampling clock. The maximum output delay at the worst SS process corner simulation was only 1534 ps. The average offset voltage by running 1 000 Monte-Carlo simulations was as low as 153 mV. Compared with other comparators, the proposed dynamic comparator had obvious advantages in the performances of voltage offset and high speed delay.

A high speed DDC system with 1, 2, 4, or 8 times optional decimation ratio was designed by analyzing the principle of the common digital down converter system. The mixers and filters of the system were optimized. A radix-4 Booth encoder and a 4-2 compressor were used in the mixers to shorten the critical path. A CSD coding based on the sharing of sub-expressions and Horner rule was utilized at the filters to reduce the hardware consumption. The digital down-conversion system was designed for a four-channel 560 MHz 14-bit time-interleaved analog-to-digital converter (TIADC), and the function verification was completed based on FPGA. The results showed that the SFDR of the I/Q signals was above 90 dB when the input signal frequency was 380 MHz and the decimation ratio was 8.

With the rise of big data, cloud computing and the internet of things, terminal devices face great challenges in hardware and power. The demand of new high efficiency low power operation unit is becoming more and more urgent. A novel Booth multiplier with high efficiency and low power consumption was proposed to solve the problem of high power consumption of operational units. It could be used in image processing, multimedia processing, pattern recognition and other fault-tolerant applications. Experimental results showed that compared with the existing Booth multipliers, the proposed approximate Booth multiplier reduced the power consumption and delay by 19.3% and 28.6% respectively, and saved area by 29.0%. Meanwhile the approximate Booth multiplier also had some advantages in operation accuracy. Finally, the validity of the proposed approximate Booth multiplier was verified in the application of Gaussian filtering.

Due to the obvious multi-scale effect of the through silicon via (TSV) and the microbump structure, a large number of meshes need to be generated during mechanical simulation modeling of 3D packaging microsystem. Resonable equivalent processing could reduce the mesh number and improve simulation efficiency. However, the actual microstructure shape may be lost, resulting in larger simulation errors when the conventional equivalent method of square column was applied. Thus, determination methods of the homogenization model parameters were proposed for actual microstructure shapes. Based on the elastic mechanics theory, the equivalent calculation methods of various material parameters of cylindrical structures such as TSV interposer layer were derived in this paper. Further, by using the derived results and based on the delamination idea, the equivalent calculation method of material parameters after homogenization of microbump/underfill layer with drum ball morphology was given. Compared with the existing methods, the proposed method considered the true morphological characteristics of microsystem structures, so the calculation efficiency was higher, and the consistency of the results was better.

According to the microwave test requirements of RF multi-port devices, a four port electronic calibrator based on RF MEMS switch with a working frequency in the range of DC~12 GHz was designed based on SOLT calibration principle. The numerical simulation results showed that the return loss of the device was less than 015 dB in the short circuit state. In the through state, the insertion loss of the device was less than 05 dB, and the isolation between ports was greater than 20 dB. In the open circuit state, the return loss of the device was less than 03 dB, and the isolation between ports was greater than 25 dB. At the same time, the load resistance was prepared by micro surface machining process and magnetron sputtering process. The tested resistance was about 50 Ω, which met the design requirements. The designed four port calibration device based on RF MEMS switch had the advantages of good RF performance, small volume and easy to integrate. It could meet the application requirements of X-band microwave multi-port devices in on-chip testing.

SiC power device has developed into a leader in the field of high voltage power devices. However, the high density interface states at the interface between SiC and SiO2 restricts the electrical properties of the SiC. Although manufacturers have adopted different gate oxidation processes to improve the channel mobility of the inversion layer, the corresponding interface states simulation model is not provided. Besides, the various interface state energy level distribution model, given by the device simulation software, causes choice dilemma for the device-designers of power devices. Thus, this paper provided an distribution model of interface state energy level for SiC MOSFET device simulation based on actual process data and TCAD simulation software. In the aid of the given model combined with TCAD software simulation, the I-V curve obtained by the simulation basically coincided with the test curve of the actual product.

Traditional silicon piezoresistive pressure sensors have disadvantages such as susceptibility to temperature, poor fracture toughness and limited sensing nodes. Therefore, a graphene pressure sensor with the suspended array structure was designed in this paper. First of all, the structure and the principle of the sensor were analyzed, and then the strain effect on the band gap of graphene was studied. Finally, the pressure amplification model and the deflection amplification model of the roof-pillar structure were established. The theoretical and simulation results showed that the pressure amplification coefficient and the radius ratio met the negative exponential relationship. Specifically, as the radius of the pillar continued to decrease, the amplification coefficient tended to a constant value. In the concentrated pressure model, the maximum deflection and the radius ratio approximately satisfied the linear relationship, and the maximum deflection had a one-third power relationship with the pressure.

A surface superjunction lateral insulated gate bipolar transistor (SSJ LIGBT) based on bulk silicon was proposed. In order to improve the device performance, the effects of the parameters, injection dose and energy， were analyzed. The structure and the termination of SSJ LIGBT were designed and optimized due to the requirement of withstand voltage. The breakdown characteristics, output characteristics and transfer characteristics of the SSJ LIGBT were tested. The test results showed that the SSJ LIGBT had a voltage resistance of 693 V and a specific on-resistance of only 6.45 Ω·mm2.

Due to the immature of the p-type GaN IMPATT manufacturing process, an In04Ga06N/GaN n-ntype heterostructure was proposed to replace the conventional p-n structure, and made the GaN IMPATT diode work in IMPATT mode. The noise characteristics of the n-n type In04Ga06N/GaN IMPATT diode were studied and compared with the conventional GaN based p-n junction IMPATT diode under the same conditions. The results showed that the noise characteristics of the device with different bias current density and different thickness of InGaN layer were better than those of conventional p-n structure. Combined with the RF output characteristics of the device, it could be found that the In04Ga06N/GaN homo-heterojunction IMPATT device was not only superior to the GaN p-n structure in power and efficiency, but also superior to the conventional GaN p-n structure in noise performance, especially in the high frequency band. This work could provide more ideas and references for the design of GaN based IMPATT devices.

The single event response characteristics of three 1 200 V trench gate SiC MOSFETs with different structures, including the conventional trench gate MOSFET, the double trench MOSFET and the asymmetric trench MOSFET, were studied and analyzed by using Sentaurus TCAD simulation software. The simulation results showed that the SEB SOA of the double trench MOSFET was superior than other two devices during the single event process. The advantage of double trench MOSFET was mainly related to the deep source trench structure, which contributed to the fast collection of the huge carriers generated by the heavy ions collision and suppressed the electrothermal coupling effect from current concentration. Moreover, compared with other two structures, the internal electrothermal coupling effect due to the huge carriers accumulation could be suppressed effectively. This effect was believed to be the main destroying mechanism related to the single event burnout.

The lateral double diffused MOSFET silicon controlled rectifiers(LDMOS~~SCR) device structure was commonly used for electrostatic protection at high voltage due to excellent high voltage characteristics. The N+ of the floating drain pole was divided into symmetric P+, N+ and P+ structures, and a dual directional protection of power device based on LDMOS~~SCR with low trigger and high holding voltage was proposed. It reduced the emitter-injection efficiency of parasitic bipolar transistors formed at the bottom of the grid region, and the inherent positive feedback mechanism of the SCR was reduced. Based on TCAD simulation, the experimental results showed that, compared with the traditional LDMOS~~DDSCR, the trigger voltage of the new device was reduced from 69.6 V to 48.5 V, and the holding voltage was increased from 14.9 V to 17 V. It was proved that the new structure had a good immunity ability of latch-up effect compared with the traditional LDMOS~~DDSCR device.

An effective measurement method for gate charge characteristics of MOSFET under high power was proposed. During the turn-on process of the lower transistor in a half-bridge circuit, a large drain current and a high drain-voltage would occur, producing a much high transient power. For the traditional test technique, not only an equal high power is required for the DC source used, but also a serious self-heating effect cannot be eliminated. Both of them lead to inaccurate gate charge curves. In this paper, based on the basic physical process and relationship of gate charge test, the gate charge characteristics of MOSFET under high power were obtained by measuring the characteristics of gate charge under high voltage-small current and high current-small voltage. The results showed that the characteristic curve and the parameters obtained by this proposed method were nearly close to the values given by the standard specification, which had good industrial application value.

A fabrication method of ring resonator based on anode bonding was designed to simplify the fabrication process of ring electrostatic gyro resonator. Silicon-based ring gyro resonators were fabricated using SOI with (100) and (111) top layers of silicon by anode bonding process. The generation of frequency splitting and its influence on gyro performance were analyzed theoretically. Meanwhile, the influence of crystal orientation on the double-and third-antinode mode was analyzed by software simulation. The matching degree of the double-and third-antinode operating modes with each crystal orientation was discussed. The amplitude-frequency response characteristics of the two devices were obtained by using network analyzer in vacuum chamber. The electrostatic force tuning method was illustrated to show how mode-matched operation can be done by adjusting dc voltages to get a new resonant frequency of (111) silicon-based ring gyro resonators..

For the needs of modern communication and phased-array radar applications, a Ka-band 4-bit switched-line RF MEMS phase shifter with a phase shift interval of 22.5° was developed. The four phase shifting units, which primarily realized the phase shifting function, were designed to provide the best impedance matching by optimizing the division of the upper and lower paths of the phase shifting units to select the pass by using the step compensation technique. Using a right angle corner structure, a delay line that improved the performance of the CPW right angle was designed, and a general design of a 4-bit switched-line phase shifter applied with this delay line was presented. Modeling and simulating with HFSS showed that the insertion loss of all 16 states was less than 2.15 dB, the return loss was greater than 19.18 dB, the VSWR was less than 1.25, the phase shift error at 40 GHz was within 1.57°, and the overall size was 10 mm2 in the 0~40 GHz operating band.

In order to solve the problem of thermal expansion coefficient (CTE) mismatch failure of a large-size CLCC device after 100 times,-45 ℃~85 ℃ temperature cycling tests, two optimization schemes were proposed to improve the CTE mismatch, and the simulation comparison analysis was carried out. Based on the improved scheme, the fatigue life was calculated by finite element simulation and Engelmaier model, and the temperature cycling test was completed. The simulation results showed that the CTE mismatch between alumina ceramics, solder and FR4 substrate could be understood better by using the lead with proper brazing parameters in the middle of ceramic, which could meet the practical requirements. This study had a reference value for the design of large size alumina ceramic package.

Compared with different thermal fatigue life prediction models of the packages, the life prediction model suitable for microcoil spring ceramic column grid array (CCGA) packaging was determined. Then the thermal fatigue mechanism of solder column was analyzed. Workbench was used to study the thermal fatigue of solder column under temperature cycle. Compared with the results of different thermal fatigue life prediction models, it showed that prediction model based on strain energy density was more suitable for microcoil spring CCGA. Then, the curves of equivalent stress, plastic strain, average plastic strain energy density and temperature with time were discussed. It indicated that the solder joints reduced its internal thermal stress level and the accumulation of thermal fatigue damage through plastic deformation or energy accumulation at temperature holding stages. At temperature transition stages, the stress and strain of solder joints changed sharply, which was intend to produce thermal fatigue damage.

AuSn alloy is widely used in silicon-based chip welding application because of its good thermal and electrical conductivity. The relationship of welding process parameters on the diffusion of silicon atoms to AuSn alloy was studied. The mass percentage of silicon atoms in AuSn solder increased by an order of magnitude when the welding temperature increased from 310 ℃ to 340 ℃. The diffusion mechanism of AuSn solder was analyzed. The influence of silicon atom diffusing into solder on product reliability and control measures were discussed.

Wire tail defects exposed in ultrasonic wedge bonding on automatic heavy wire bonder were examined, and the generating mechanism of wire tail was analyzed. A wire tail fault tree was set up, a tail defects’ fishbone diagrams was built, and a relationship matrix between the phenomenon of tail wire defect and its root cause factors was proposed. The key factors and requirements of tail quality controlling were established.