The electrostatic discharge (ESD) protection requirements of integrated circuits with operating voltage of 5 V can be met by the trigger voltage of the low-voltage triggering silicon controlled rectifier (LVTSCR), but the LVTSCR’s low holding voltage always lead to severe latch-up. In order to solve the problems of latch-up, the improved LVTSCR was proposed. An N-type heavily doped buried layer was inserted below the N type well, which changed the current flow path after LVTSCR triggered and reduced the accumulation of holes in the substrate. Thereby the Webster effect of the LVTSCR was inhibited and the holding voltage was increased. Sentaurus TCAD simulation results showed that the holding voltage of the proposed device was increased from 2.44 V to 5.57 V without increasing the additional area, which could avoid the latch-up effect of the integrated circuit with the working voltage of 5 V.