Based on the traditional asynchronous FIFO circuits, a controllable delay asynchronous FIFO circuit structure was designed. The delay control module was added to the circuit while realizing the data transmission across clock domain. The integral delay was controlled by adjusting the difference between the read pointer and the write pointer, and the fractional delay was controlled by adjusting the phase difference between the read clock and the write clock. The VCS verification platform was established for functional verification. The results showed that data transmission across clock domain and delay dynamic control could be achieved in this FIFO circuit. The output skew caused by data source misalignment could be compensated when multichips worked at the same time. Based on a 180 nm standard CMOS process library, the read clock frequency was 389 MHz, and the write clock frequency was 778 MHz. The logic resource area was 41 071 μm2.