A 56 Gbit/s PAM4 optical receiver front-end was designed in a 65 nm CMOS process. A transimpedance amplifier (TIA) used a common-gate feedforward structure to reduce the input impedance, and an inductor was added at the input port to improve the bandwidth and sensitivity at the input of TIA. A multi-stage variable gain amplifier (VGA) with linear gain control was adopted to adjust the output swing automatically at the post stage. The output buffer (OB) employed the source degeneration technique so as to expand the bandwidth. The post-simulation results showed that the -3 dB bandwidth was 24.4 GHz, the maximum gain reached 66 dBΩ, and the input-referred noise current was 17.0 pA·Hz-1/2 with 100 fF photodiode capacitance. Under different process corners and input currents, the output eye-diagrams had small jitter and fine opening degree. The average power consumption was 42.5 mW at different process corners from a voltage supply of 1.2 V.