Semiconductor technology is the main driving force for the future development of information and communication technologies, and analog electronics is an integral part of semiconductor technology. Several major technology trends in analog electronics technology in terms of sensing and execution intelligence, new computational processing architectures, high energy efficiency, and overall collaborative development platforms driven by higher demands such as greater processing, transmission capabilities and low latency sensing for future information systems were described in this paper. The important research directions of analog electronic technology in the basic level of transistor, circuit, analog learning architecture, advanced technology and communication field were discussed. This review showed the outline of key technologies for analog electronics in the next decade.

The continuous increase of peak-to-average power ratio (PAPR) makes the wireless communication terminals require power amplifiers with higher power, efficiency, and frequency. The existing analog power amplifier was the last barrier for the fully digital base station, of which efficiency and output power were insufficient to meet the needs. With the merits of high output power, speed and efficiency, GaN digital power amplifier operating at switching mode, was one of the keys to realize digital base station. The GaN digital power amplifier could still operate at a higher efficiency even for the input with high PAPR to make up for the lack of efficiency of analog power amplifier at the same situation. This paper outlined the working principle of the GaN digital power amplifier, summarized recent technological advances and challenges at home and abroad, and described the future development and optimization of the GaN digital power amplifier.

By analyzing the problems of long-term "follow-up design" of chinese core components, the concept of independently-defined components was proposed, and the classification method for independently-defining the core components was given. Based on the classification of the component’s independent definition, the implementation approaches and key technologies were presented. Meanwhile, by analyzing the implementation cases of independent defined core components at different levels, relevant suggestions for carrying out independent definition of core components were summarized in the end.

A four-channel 8-bit 216 GS/s time-interleaved successive approximation register analog-to-digital converter (TI-SAR ADC) was designed. A dual-loop structure with an asynchronous clock loop and a data loop was explored to achieve high speed operation. A dynamic comparator with reset switches was employed to shorten the quantization time and improve the comparison accuracy. A reversed monotonic switching sequence approach was utilized to increase the input common-mode voltage and improve the quantization speed. The chip was designed in a 55 nm CMOS technology. The post-layout simulation results showed that the TI-SAR ADC achieved an FOM of 212 fJ/(conv.step), an SNDR of 427 dB and an SFDR of 53 dB under Nyquist input frequency, while consuming 426 mA current from 12 V power supply. The ADC occupied an area of 34 mm2.

Based on a 180 nm BCD process, a novel high performance bandgap voltage reference without op-amp was designed, which was based on the traditional bandgap reference structure. The bandgap reference voltage was adjusted through the cascode current mirror technology and the negative feedback network to eliminate the adverse effects of the op amp offset voltage. The circuit was simulated under Cadence EDA tools of Spectre. As the simulation results showed, the output of the design was 1228 V. Within the range of temperature of -40 ℃ to 125 ℃, the temperature coefficient was 147×10-6/℃. The PSRR was -86 dB at 1 kHz, and the linear adjustment rate was 65×10-5/V.

Reconfigurable input matching adopted a L-shaped circuit structure, which was connected to a section of microstrip line through a single-pole single-throw switch circuit to realize automatic compensation of input impedance at different operating frequencies. The output matching realized concurrent dual-frequency work. The formula was re-derived on the basis of the early three-section microstrip line, and a four-section microstrip line structure in series that was easier to implement was proposed. The power amplifier adopted a reconfigurable structure combined with a concurrent dual-band matching network, so only one switch was used. The circuit structure was simple, and the switch had a small effect on circuit performance. The simulation results showed that the matching state and performance of the power amplifier were good, which provided an idea for designing the existing reconfigurable power amplifiers.

A novel energy-efficient capacitor switching scheme for high speed successive approximation register (SAR) analog-to-digital converters (ADC) was proposed. Based on the 2bit/cycle architecture, two differential split capacitor arrays were employed as the digital-to-analog converter (DAC). The proposed scheme decreased the dynamic energy consumption of the capacitor arrays and the total capacitor area while it speeded up the settling of the capacitor by one-side charging operation. During the last quantization cycle, the common-voltage was introduced only to one side of the differential arrays, and just one comparator was enabled. By these, the proposed scheme got more resolution and further decreased the dynamic energy consumption. The proposed scheme achieved an 83% reduction of the average switching energy and a 50% reduction of the total capacitor area while it almost doubled the conversion speed compared with the conventional 1bit/cycle scheme, and it got different degrees of improvement in resolution, total capacitor area and energy consumption when compared with other 2bit/cycle schemes.

A fully differential operational transconductance amplifier with high gain and high power efficiency was designed based on a novel mirror current source circuit with low voltage drop and high output resistance. The OTA was designed in a 018 μm CMOS process at 18 V supply voltage. The higher DC voltage gain was obtained on the premise of keeping 18VPP differential output voltage swing. The NMOS tube differential pairs was used as input sleeve structure. The results showed that the OTA had an open-loop DC gain of 119 dB, a gain bandwidth product of 526 MHz, and a phase margin up to 77° at 23 mA bias current and 2 pF load capacitance. The OTA’s open-loop DC gain could be increased to 153 dB when using an additional gain boost technology.

Based on a 2 μm InGaP/GaAs HBT process, a high efficiency, high linear power amplifier for LTE terminal was designed and implemented. Analog predistortion and phase compensator were used to suppress the amplitude distortion and phase distortion, so as to achieve high linearity. The second harmonic terminal capacitor was used to change the working mode of the circuit, and the overlapping power loss of voltage and current in time domain was reduced, so the additional power efficiency was improved. The results showed that the gain of the power amplifier was greater than 295 dB and the input return loss was less than -132 dB at 34 V power supply and 28 V bias voltage within 815~915 MHz frequency range. In the case of 10 MHz LTE input modulation signal and 28 dBm back output power, the power added efficiency was 39%~41%, the ACLR1 was less than -381 dBc, and the ACLR2 was less than -448 dBc.

A pico-ampere voltage reference with high precision was designed. Employing a new type of PVT (process, power, temperature) compensation method, the impact of PVT variations on the circuit performance could be effectively suppressed. Therefore, the stability and accuracy of the proposed voltage reference could be greatly improved while ensuring ultra-low power consumption. The circuit was designed in a standard 018 μm CMOS technology. The simulation results with Spectre showed that the output reference voltage was 7555 mV, the line regulation was 416×10-6/V over the supply voltage range from 09 V to 18 V, the power supply rejection ratio was -955 dB@10Hz, and the 3δ inaccuracy of reference voltage was 011%. The average temperature coefficient was 165×10-5/℃ over the temperature range from -20 ℃ to 120 ℃. The typical operating current was 347 pA at room temperature. This voltage reference had excellent performance for low-power IoT application systems.

Based on AWSC 2 μm HBT process, a power amplifier applied in 5G N77 frequency band (33～42 GHz) was designed. The gain, output power and power added efficiency of the power amplifier were significantly improved by using transformer matching. The problem of difficulty for matching the inter-stage of amplification circuits was solved. Simulation and test results showed that in the N77 operating band, the power amplifier had a gain of 36~38 dBm, an output power 1 dB compression point of 37 dBm, a power addition efficiency of 493 % at 1 dB compression point output power, a power addition efficiency of 165 % at 285 dBm output power, and an adjacent channel leakage ratio of -382 dBc.

A charge pump phase-locked loop with a locking frequency range of 16~24 GHz was designed in a 018 μm CMOS process. A high performance frequency discriminator, a charge pump and a third-order Σ-Δ modulator were adopted to reduce the reference spurs on output clocks. By introducing LFSR into the Σ-Δ modulator, a pseudo-random sequence was generated and the fractional spurs was further reduced. The simulation results showed that the current mismatch ratio was only 01% and the fractional spur was -50 dBc @1 MHz at 03~15 V output voltage.

An analog baseband (ABB) for the 24 GHz Doppler/ FMCW dual-mode radar system was designed in a 55 nm CMOS process. The low pass filter was realized by two modified Tow-Thomas bi-quad stages to adjust the gain and the bandwidth independently. In order to cancel the DC offset produced by the mixer and caused by the ABB mismatch in Doppler mode with 10~600 Hz low intermediate frequency, a two-step successive approximation register DC-offset cancellation (SAR DCOC) circuit based on a 7 bit current-programmable digital-to-analog converter (IDAC) was employed. In order to improve low frequency noise performance, the BJT devices were used in the proposed low pass filter and IDAC circuits. The post-layout simulation results showed that the proposed ABB achieved a gain from 6 to 62 dB and a maximum linear input amplitude (IP1 dB) of 10 dBm in both modes while drawing 49 mA from 25 V power supply. When the gain was 62 dB, the noise figure at Doppler and FMCW mode were lower than 42 dB and 27 dB, respectively. The Monte Carlo simulation results showed that the output DC offset were 213 mV and 164 mV while the input DC offset were 400 mV and 200 mV, respectively.

A switched current error amplifier (SC-EA) was proposed for the use of buck converters. In the buck structure, the system could be kept stable without off-chip compensation, saving chip area and obtaining higher power density. The bandwidth of the error amplifier adaptively changed with the switching frequency, and it still had good stability and fast transient response speed at high frequency. The on-chip frequency compensation was realized by using the valley current mode COT structure of the switching current mode error amplifier, and the off-chip components were omitted. The multi-channel parallel current sharing was realized, and the transient response speed was faster. The circuit was designed in a 018 μm BCD process. The simulation results showed that the loop stability and adaptive bandwidth could be achieved by selecting 10 μF and 70 μF output capacitors at 6 MHz and 1 MHz switching frequency, respectively. At the switching frequency of 6 MHz, the upper and lower step transient response time was 63 μs and 55 μs, respectively. At the switching frequency of 1 MHz, the upper and lower step transient response time was 277 μs and 284 μs, respectively.

A low noise precision operational amplifier was designed in a 40 V bipolar process, which was used in high precision and high resolution systems. The whole structure and operation mechanism of the operational amplifier were introduced. The key design techniques of operational amplifier such as reduced input bias current, reduced input offset voltage and frequency compensation were analyzed in detail. Then the operational amplifier was simulated with Spectre tool, and it was fabricated and verified. The tested results indicated that, under ±15 V power supplies, the device achieved an input bias current of 2 nA, an input offset voltage of 10 μV, a large signal voltage gain of 132 dB, a common mode reject ratio of 135 dB, and a power supply reject ratio of 130 dB. The circuit met the requirements of high precision, high resolution and low noise applications.

A digital control buck converter based on adaptive frequency DPWM was proposed for the use of fixed-frequency voltage-mode PWM control. In the load step response, the output value of the DPID changed to modulate the duty cycle of the PWM signal, and the DPWM frequency varied according to the output error value, which improved the modulation intensity of PWM signal. The change of DPWM frequency was realized by fractional frequency division and detection of ADC output. The transient response of the circuit was improved effectively by subsection regulation. The buck converter was designed in a 018 μm CMOS process. The simulation results showed that when the load current varied from 10 to 20 A, the overshoot voltage was reduced by 5 mV, the recovery time was shortened by 105 μs, the undershoot voltage was reduced by 8 mV, and the recovery time was shortened by 96 μs.

A constant on-time control buck converter using adaptive ramp compensation (ARC) was proposed. Two slope voltages were introduced to detect the falling slope of the inductor current. The compensation slope was adjusted through a negative feedback loop, so that the compensation slope followed the falling slope of the inductor current. Finally, the extra poles brought by slope compensation were fixed, making it easier to compensate the design. On this basis, the transient enhancement circuit was introduced to improve the load step response speed. Under 5 V output, when the load was stepped from 3 A to 100 mA, the output voltage overshoot was reduced by 150 mV, and the recovery time was shortened by 10 μs. When the load was stepped from 100 mA to 3 A, the output voltage undershoot was reduced by 130 mV, and the recovery time was shortened by 12 μs.

The harm of backflow current to the power tube of DC/DC power module in the flyback synchronous rectifier were studied. The causes and magnitude of the backflow current in the process of the rapid restart and shutdown of the synchronous rectifier under capacitive load were analyzed. A scheme of delayed turn-on of secondary synchronous MOSFET in start-up stage and fast turn-off in power-off stage was proposed, and the backflow current of flyback synchronous rectifier power module was controlled. A flyback synchronous rectifier module with 6 V/10 A output was designed based on this control scheme. The results of simulation and measurement showed that the inhibition effect of reverse current was obvious.

A 10 Gbit/s adaptive CTLE based on spectrum balancing was designed. The bandwidth and gain of the linear equalizer were improved by inductor parallel peaking and source degradation techniques. In order to extend the rate range of adaptive CTLE based on spectrum balancing, the cut-off frequency of low frequency and high frequency was adjusted simultaneously by the active hybrid filter. Meanwhile, the mismatch error was reduced by DC offset cancellation loop (DCOC). The simulation was carried out by TSMC 018 μm CMOS process. The results showed that the 10 Gbit/s PRBS7 signal was transmitted through an 4572 cm FR4 backplane with a loss of 15451 dB at the Nyquist frequency, and after equalization with equalizer, the eye opening reached 05 UI.

An efficiency-enhanced circuit for buck converter in discontinuous conduction mode was presented in this paper. Based on the detailed analysis of the critical factors affecting the conversion efficiency, a novel rectifier-driven control scheme was researched. The proposed technique had the function of adaptive dead-time and zero-current detection, for the purpose of maximized efficiency by optimizing the power losses caused by body-diode conduction and reverse inductor current, while taking into account the system power consumption. The circuit had been designed and simulated in a 018 μm BCD process. The simulation results showed that the proposed design achieved a peak efficiency of 966% and a high power conversion efficiency of >90% for load currents greater than 5 mA, when the input and output voltage was 3 V and 15 V respectively.

A novel power clamp circuit was proposed, which aimed to solve the problems of large leakage current, false triggering, and low on-time in traditional circuits. This circuit used the current amplification of a bipolar transistor (BJT) to reduce the capacitance value, and the feedback function of a MOS tube and a series diode was used to adjust the trigger voltage. In this way, the performance of the clamp circuit could be improved. The simulation results showed that the circuit could quickly respond to ESD events, and could achieve a fast shutdown function, thereby quickly discharging current and avoiding damage to the internal circuit.

In response to the application requirements of broadband width, low insertion loss and low power consumption of switches proposed by satellite communication, electronic countermeasures and microwave test systems, a wide band RF MEMS switch for the K~D band was designed. The bandwidth of the switch was improved and the loss of the switch was reduced by optimizing the substrate material and the cross-shaped upper electrode structure. The HFSS electromagnetic wave simulation software was used to optimize the geometric parameters of the switch. The results showed that the designed RF MEMS switch could work in the frequency band of 18~188 GHz, the insertion loss was less than 147 dB, the isolation was more than 2012 dB, and its overall volume was about 075 mm3. This switch could be integrated with phase shifters, delay lines, resonators and other devices to realize broadband and low-loss RF reconfigurable MEMS devices and systems, which were used in the fields of next-generation communications and microwave testing.

Multiple baking equipment would be used in the microelectronic assemble process to implement the integrated monitoring of the equipment, which could improve the process efficiency, quality control level and the safety level of equipment operation. In the monitoring system, RS485 communication was adopted, PLC collected data and controlled on site, and the computer was used as the upper computer for monitoring and data information processing. The monitoring system operated in a complex industrial site with serious electromagnetic interference, which was easy to cause data errors, false alarm and even system paralysis. The anti-interference design should be carried out in the design of integrated monitoring system, and its analysis and design was a difficult point. According to the characteristics of process operation of a few baking equipment, hardware anti-interference design such as RS485 communication with strong anti-interference and separately wiring of electrics and electronics was adopted in this paper. A anti-interference design software based on the simple process stage classification processing method was provided, thus the stable operation of the integrated monitoring system of multiple baking equipment for micro-assembly had been realized.

In order to solve the problem of high resource consumption and low precision in the hardware implementation of the activation function Tanh, a Tanh function approximation algorithm combining second-order approximation and error compensation was proposed. This method first performed log2 transformation on the traditional second-order approximation function’s coefficients, which was convenient for hardware implementation and reduced the resource consumption. Then the compensation interval was divided according to the approximate function’s error curve to improve the function’s accuracy. On this basis, the circuit structure of the hardware implementation of the Tanh function was designed. The ModelSim platform was used for functional simulation, and the logic synthesis was performed under the SMIC 018 μm process. Experimental results showed that the implemented circuit’s maximum absolute error was 0007 8, which was the highest accuracy that the 8 bit output width could represent.

An all-digital adaptive background algorithm for calibrating the channel mismatch error of the time-interleaved analog-to-digital converter (TIADC) was proposed. The algorithm used the Walsh function to modulate and generate the spurious signal only from the output of the TIADC, which could reconstruct the mismatch error and adaptively subtract three mismatch errors from the TIADC output. The advantage of the proposed technique was that it only needed to know the output signal of measurement and the number of TIADC channels without any other information including the reference channel. At the same time, aimed at the problem that the algorithm (most modulation algorithms) was unable to calibrate special frequency points, a frequency judgment module was designed in this paper, and extra spurs of special frequency points was eliminated by a set of low-pass filters and band-pass filter, which overcame the limitation of the algorithm. Simulation results showed that the proposed technology could effectively eliminate the channel mismatch errors, thereby greatly improving the performance of the TIADC system.

The breakdown characteristics of 4H-SiC JBS diodes with a JTE termination was studied. First, the impacts of the ion implantation dose, lateral length and interface charge of the JTE terminal on the breakdown voltage were analyzed by simulation. The experimental samples were fabricated based on the optimized process parameters. The measurement results showed that the forward threshold voltage was 152 V, the specific on-resistance was 212 mΩ·cm2, and the breakdown voltage was 1 650 V. The forward current was mainly thermal emission mechanism, while the reverse current had strong voltage and temperature dependence. Finally, the high temperature reverse deviational stress aging test was carried out, and the results showed that the breakdown voltage showed a downtrend.

An In04Ga06N/GaN homo-heterojunction IMPATT diode was proposed. Due to the immature P-type GaN manufacturing process, this research scheme could be taken as an alternative scheme for GaN based IMPATT diode. For comparison, the DC and AC characteristics of both In04Ga06N/GaN heterojunction IMPATT and PN junction IMPATT diode were studied in detail. The results showed that the performance of In04Ga06N/GaN IMPATT diode was better than that of traditional PN junction IMPATT diode without P-type GaN.

In modern high performance analog integrated circuits, 1/f noise is one of the key issues affect the circuit performance. The effects of emitter structure on DC and low frequency noise characteristics in double polysilicon self-aligned high speed complementary NPN bipolar transistors was studied. It was demonstrated that the interfacial oxide layer between polysilicon emitter and monocrystalline silicon and the emitter geometry were the major factors which greatly affect the 1/f noise characteristics.

With the development of smart energy metering, more electronic components are utilized in electricity systems. The electronic devices are important for electric power measurement system, which can improve or deteriorate the precision and reliability of systems. So evaluation screening for components has become an effective way for incoming material quality management in energy metering systems. In order to achieve reasonable screening method and ensure the long-term reliability of electronic measurement equipment, the relevant test data of devices was analyzed according to testing standards and statistical methods in this paper. A rapid screening method for lithium/thionyl chloride batteries based on the analysis of measurement data of battery passivation characteristics was proposed.