A low-voltage low-power CMOS ring oscillator with pseudo-differential structure was designed in the TSMC 28 nm CMOS process, which included oscillator’s bias circuit, ring oscillator and output buffer. The pseudo-differential ring oscillator utilized a five-stage delay unit with a Maneatis symmetrical load to improve the VCO’s tuning linearity and tuning range. Pre-simulation on Cadence Spectre showed that when the VCO was operating at 0.9 V supply voltage, the frequency tuning range was 0.65 GHz to 4.12 GHz. The tuning linearity was excellent in the most area of tuning range. With a center frequency of about 2.3 GHz, the phase noise was -79.06 dBc/Hz@1 MHz. The output buffer stage enabled the rail-to-rail output swing and the duty ratio of 50%. The power consumption of the ring oscillator was approximately 5.7 mW.