Xiaojun Fu

Jan. 01, 1900
  • Vol. 51 Issue 2 1 (2021)
  • ZHANG Zheng, ZHANG Yanhua, HUANG Xin, and NA Weicong

    A multiband low noise amplifier (MBLNA) based on high performance tunable active inductor (TAI) was studied. At amplifier stage, the frequency selection network was constructed by the TAIs with tunable inductance and Q value, and by the variodes with tunable capacitance. It could selectively amplify the signals in different frequency bands in conjunction with common-emitter common-base amplifier circuit. At input stage, the common-emitter amplifier circuit with input inductor in series and emitter inductor negative feedback was employed to realize the broadband input matching. At output stage, the common-emitter amplifier circuit was used to meet output matching and high gain of MBLNA. Furthermore, the current reuse of output stage and amplifier stage reduced power consumption of LNA. Based on WIN 0.2 μm GaAs HBT process library, the performance of MBLNA was verified by ADS. The results indicated that the MBLNA could operate at 1.9 GHz, 2.4 GHz, 3.4 GHz and 5.2 GHz, the voltage gain S21 at above bands reached 27.2 dB, 25.5 dB, 21.6 dB and 17.4 dB respectively, the noise figures (NF) were in the range of 1.3 dB~5.2 dB, the good input and output matching was achieved, and the power consumption was only 17.5 mW.

    Jan. 01, 1900
  • Vol. 51 Issue 2 151 (2021)
  • HUANG Zhengfeng, LI Xueyun, YANG Xiao, QI Haochen, LU Yingchun, WANG Jian’an, NI Tianming, and XU Qi

    A radiation hardened 12T SRAM memory cell was presented. The stack structure composed of NMOS tubes was adopted to reduce power consumption, and the single event upset characteristic was used to reduce sensitive nodes, thus achieving good reliability and low power consumption. Hspice simulation results showed that the proposed memory cell could fully tolerate single node upset, and partially tolerate double node upset with a ratio of 33.33%. Compared with other ten memory cells, the area overhead of the proposed memory cell was increased by 3.90% on average, and the power consumption, read time and write time were reduced by 34.54%, 6.99% and 26.32% on average. The circuit had a large static noise margin with good stability.

    Jan. 01, 1900
  • Vol. 51 Issue 2 157 (2021)
  • WANG Yuanfei, LUO Ping, YANG Jian, TANG Tianyuan, and YANG Bingzhong

    A high performance sub-threshold CMOS voltage reference was designed in a 0.18 μm CMOS process. A voltage subtraction circuit working in the sub-threshold region was proposed, which adopted the gate-source voltage difference of two transistors with different threshold voltages as the voltage reference output. At the same time, the proposed voltage subtraction circuit could well eliminate the influence of the power supply voltage change on the output reference. The post-simulation results showed that the voltage reference designed in this paper had a linear sensitivity of 0.053%/V~0.121%/V in the supply voltage range of 0.55~1.8 V, the temperature coefficient was 9.5×10-6/℃~3.49×10-5/℃ in the temperature range of -20 ℃ ~80 ℃, the power supply rejection ratio was -65 dB@100 Hz, and the power consumption was 3.7 nW @tt, 0.55 V. The chip area was 0.008 2 mm2. The circuit was suitable for low power applications such as energy harvesting and wireless sensors.

    Jan. 01, 1900
  • Vol. 51 Issue 2 163 (2021)
  • GUO Liang, ZENG Tao, HUANG Feilin, LEI Langcheng, SU Chen, LIU Fan, and LIU Luncai

    A high speed sample and hold (S/H) circuit using low threshold technology was presented. Capacitor flip-around architecture was used for S/H circuit. Gate-bootstrapped switch technique was used to improve linearity. Bottom-plate sampling technique was adopted to reduce charge injection effect. The proposed amplifier and the traditional telescopic common-source common-gate amplifier had the same circuit structure. What’s the difference was that the proposed amplifier used a low threshold technology with the advantages of high gain and bandwidth by adopting low threshold device compensation based on a specific process, and it improved the sampling rate of the sample-and-hold circuit. The circuit was designed and fabricated in a 0.18 μm CMOS technology, and the sampling clock frequency was more than 125 MHz. The simulation results showed that SINAD was 90.91 dB, SFDR was 91.45 dBc, and the chip area was 0.8 mm×0.5 mm.

    Jan. 01, 1900
  • Vol. 51 Issue 2 168 (2021)
  • WANG Zijian, and HUANG Jiwei

    Based on a 0.18 μm CMOS process, a wideband low noise amplifier(LNA)applied in direct RF sampling (DRFS) receivers at VHF was designed. In order to solve the problems of large area and difficult integration caused by using inductor at VHF, an inductorless structure was adopted, so the circuit had the function of single input and double output. In order to reduce noise, a noise cancellation structure based on cascode negative feedback was adopted. The post-simulation results showed that the whole circuit’s input matching parameter S11 was less than -15 dB, the output matching parameter S22 was less than -12.6 dB, the gain was 25.22~25.39 dB, and the noise factor was less than 1.927 dB within 30~300 MHz. The Layout size was 204 μm×365 μm.

    Jan. 01, 1900
  • Vol. 51 Issue 2 173 (2021)
  • WAN Hezhan, ZHANG Wanrong, XIE Hongyun, JIN Dongyue, NA Weicong, ZHANG Sijia, and ZHANG Zhao

    A new type of differential active inductor based on LC parallel resonant circuit was proposed, which could achieve wide operating frequency band, high Q value, large inductance value and tunable performance. The LC resonant circuit was composed of passive inductor and variable capacitor of MOS transistor, which reduced the equivalent series resistance and equivalent shunt capacitance, and enlarged the working frequency band while increasing the inductance and Q values. The simulation results showed that the inductance value was greater than 26 nH and the Q value was greater than 138 at 2~ 7.6 GHz for the new differential active inductor. The inductance value was up to 130 nH, and the Q value was up to 418 at 7.6 GHz high frequency, so this inductor achieved high Q value and high inductance at wide operating band range. Compared with traditional differential active inductors and single-ended active inductors with LC resonant circuit, the performance of this new differential active inductors was better.

    Jan. 01, 1900
  • Vol. 51 Issue 2 179 (2021)
  • ZHAO Zhong, LUO Ping, LIU Lei, LIU Junhong, and YANG Bingzhong

    To solve the problem of narrow operating frequency of traditional adaptive on-time control DC-DC converter, an adaptive timing circuit for wide-frequency application was proposed. Based on the DC-DC converter with PLL modulation, the current of the oscillator was introduced into the timing circuit through a full CMOS current multiplier. The center frequency of the timing circuit could follow the frequency of the oscillator, so the adaptive on-time control DC-DC converter could work in a wide frequency range. The adaptive timing circuit was simulated by 0.18 μm BCD technology. The results showed that the frequency range of the DC-DC converter using the adaptive timing circuit was 0.27~3 MHz.

    Jan. 01, 1900
  • Vol. 51 Issue 2 183 (2021)
  • DENG Chengda, LUO Ping, TANG Tianyuan, and WANG Qiang

    Based on topological structure of primary side feedback flyback converter, a dynamic regulation leading edge blanking circuit suitable for PWM、PFM regulation mode was proposed. First, when the system was working in PWM or PFM mode, the output current information and the system operating frequency were detected respectively to generate the dynamically regulated front blanking signal, which avoiding the miss-sampling of knee voltage caused by high frequency oscillation of the auxiliary winding. Secondly, the front blanking time was dynamically adjusted to reduce the power consumption of the lap sampling circuit in the full load range. The designed sampling circuit could obtain the output current information and the working frequency information of the system, which avoiding the miss-sampling of the knee voltage caused by the nonlinear adjustment of the blanking time when working conditions of the flyback converter were changed. The circuit was designed in a 0.18 μm BCD process. The simulation results showed that the minimum error of dynamic regulation leading edge blanking time was 4%.

    Jan. 01, 1900
  • Vol. 51 Issue 2 188 (2021)
  • HUANG Changhua, ZHANG Ying, LIU Kai, and MA Qian

    An octal amplitude shift keying (ASK) modulation circuit working at 10 GHz was designed in a 0.18 μm CMOS process. By using the structural characteristics of distributed amplifier, a set of switches were added to change the signal transmission path and control the amplitude and phase of the output signal, and the octal amplitude shift keying modulation of the signal was realized, which effectively improved the frequency band utilization of the signal transmission. The simulation results showed that the data rate of the modulation circuit could reach 3 Gbit/s with the carrier frequency of 10 GHz, and the energy consumption per bit was 12 pJ. The average power consumption was 36.35 mW.

    Jan. 01, 1900
  • Vol. 51 Issue 2 194 (2021)
  • YUAN Jun, ZHOU Yi, MAO Dingchang, CHIO U Fat, and WANG Wei

    In order to solve the problems that the conversion efficiency of PWM DC-DC dropped sharply at light load, a PWM DC-DC circuit with a segmented output stage was proposed, which was used to optimize the conversion efficiency of light load. A load current detection circuit was introduced to sample and detect the output current. When the load was heavy, all power MOSFETs were output at the same time. When the load current was reduced, the power MOSFETs were turned off from the first stage to the second stage gradually, until the smallest size power MOSFET was only working in the lightest load. The simulation results showed that within a load range of 1~200 mA, the conversion efficiency of the proposed DC-DC converter changed more smoothly. At the light load of 1 mA, the conversion efficiency of the circuit was 81%.

    Jan. 01, 1900
  • Vol. 51 Issue 2 198 (2021)
  • GUO Xinzhen, YANG Xiao, and GUO Yang

    As the feature size of the integrated circuit devices is reduced further, the distance among the internal nodes of the latch becomes shorter and shorter. Due to the charge sharing effect among internal nodes, single event upset (SEU) affected nodes that frequently occurred in the space radiation environment have expanded from single nodes to double nodes. A new hardened latch structure which used the inherent hold property of the C-element was proposed in this paper. A complete tolerance to single node upset (SNU) and double node upset (DNU) was realized. HSPICE simulation results showed that, compared with other similar hardened designs, the power consumption of the proposed latch had decreased by 34.86% on average, the delay had decreased by 59% on average, and the power delay product had decreased by 67.91% on average. PVT analysis showed that the proposed latch structure was not sensitive to the changes in voltage, temperature and manufacturing processes.

    Jan. 01, 1900
  • Vol. 51 Issue 2 203 (2021)
  • LI Bo, LI Jianzhuang, GAN Xuchun, and HUANG Xiaozong

    A kind of electrostatic discharge (ESD) protection technology using system in package (SiP) was presented. A SiP ESD protection circuit was realized by using TVS diodes to construct a reasonable ESD current discharge path. The anti ESD capability of core chip was improved from HBM 2 000V to 8 000V. Compared with the on chip ESD protection technology, the SiP ESD protection technology could significantly improve the ESD ability, shorten the design cycle, and be compatible with the original chip package size, which could be widely used in the product of SiP circuit.

    Jan. 01, 1900
  • Vol. 51 Issue 2 211 (2021)
  • PENG Xiong, LIU Tao, CHEN Kun, and QIAO Zhe

    A symmetrical SPDT switch working at 28 GHz was designed in a 55 nm CMOS process. The series-parallel structure was used to realize high isolation. The LC impedance matching was carried out by the switch inductor composed of MOS transistor and inductor, so as to achieve low insertion loss and small chip area. The body-floating technology was used to improve the insertion loss and linearity. The simulation results showed that the insertion loss of the SPDT switch was less than 1.7 dB, the isolation was more than 30 dB, the return loss of the input and output was less than -20 dB, and the input 1dB compression point was 12 dBm. The chip size was 240 μm ×180 μm.

    Jan. 01, 1900
  • Vol. 51 Issue 2 216 (2021)
  • ZHANG Lin, LI Jing, FU Dongbing, WAN Xianjie, and DING Yi

    Polysilicon fuses are one time programmable non-volatile memory elements which are allowed to calibrate the integrated circuits to assure the circuit’s performance stability at PVT corners. Based on the improvement of a traditional architecture of fuse trimming circuit, a kind of highly reliable silicided polysilicon fuse trimming circuit under normal blowing voltage was designed, which benefited from low power consume, easy to expand and strong versatility. This fuse trimming circuit was fabricated in a 0.25 μm CMOS process. The tested results showed that, under 3.3 V blowing voltage, the fuse trimming of 14 bit DAC’s high 31 thermometer current sources was successful.

    Jan. 01, 1900
  • Vol. 51 Issue 2 221 (2021)
  • LIN Kang, ZHANG Ling, YU Zongguang, CHEN Zhenjiao, and XUE Haiwei

    Synchronous mutual exclusion between different data is an important factor affecting the communication between multi-core processor cores. In order to improve the communication efficiency between different data nodes, reduce the delay of communication, and reduce the loss of data transmission,combining Adaptive Random Early Detection (ARED) algorithm and Binary Exponential Backoff (BEB) algorithm, a management allocation method of synchronous mutual exclusion that was combining software and hardware was proposed. The feasibility of the two algorithms was analyzed by Matlab modeling, and the synchronous mutual exclusion management allocation method was transplanted to the ZYNQ7000 development platform for simulation testing. The test results showed that the communication mechanism had a lower packet loss rate and delayed time, which improved the efficiency of overall transmission and reduced the delayed time of communication process.

    Jan. 01, 1900
  • Vol. 51 Issue 2 225 (2021)
  • ZUO Wen, ZHANG Congchun, XIE Jiacheng, and WANG Debo

    The microwave characteristics of coupled MEMS microwave power sensor could be analyzed and calculated by the lumped parameter model, which had become an important reference for the design of sensor’s structure and size. For the increasingly complex impedance matching structure of sensors, the lumped parameter model of the sensor was optimized and derived in this work. The measurement results showed that the maximum calculated error of reflection coefficient was 6.0 dB, and the insertion loss was 0.7 dB. The accuracy of the model was obviously improved after the optimization. Therefore, the lumped parameter model optimized in this work had certain application value and reference significance for the design and optimization of coupled MEMS microwave power sensors.

    Jan. 01, 1900
  • Vol. 51 Issue 2 230 (2021)
  • ZHANG Sanfeng, ZHOU Xiong, and LI Qiang

    Through modulation and demodulation, the chopping technique could effectively reduce amplifier’s input referred noise and offset, and improve the common-mode rejection ability. Therefore, it had been widely used in high-performance analog front-end design. Due to the up modulated offset and low frequency noise, large ripple appeared at the output of the amplifier, which required additional filtering process. An introduction of working principles of chopper amplifiers and mechanisms of output ripple were presented in this paper. A review of state-of-the-art ripple rejection techniques was given, which provided a useful reference for designers adopting the chopping technique.

    Jan. 01, 1900
  • Vol. 51 Issue 2 235 (2021)
  • LIAO Xiyi, DENG Li, and GAO Zhenkui

    A method for improving the reinforcing quality of the surface mount components with glue was introduced. The key indexes to characterize the adhesive reinforcement process quality of surface mount elements were summarized. Based on the indexes, the orthogonal experiment was studied. According to the results, the reinforced component’s adhesive-force was improved and had high consistency. Moreover, some differences in the glue morphology and the influence of glue flowing on the nearby components were observed before and after improvement. The mechanism of reinforcing components with glue was discussed around the mainly factors.

    Jan. 01, 1900
  • Vol. 51 Issue 2 240 (2021)
  • CHEN Weizhen, and CHENG Junji

    An Insulated Gate Bipolar Transistor (IGBT) with a trench filled with high permittivity dielectric was presented. The effect of high permittivity dielectric modulation was analyzed. The results showed that, compared with the field stop IGBT, the breakdown voltage of the proposed device was increased by 8%, the on-state voltage and turn-off loss were decreased by 8% and 11%, respectively. At the same on-state voltage drop, the turn-off loss of the device was reduced by 35%. Moreover, by adding another dielectric between gate and the previous HK dielectric, the performance of the proposed device could be enhanced further. Compared with the common field stop IGBT, the turn-off loss of the modified device was reduced by 57% at the same breakdown voltage and on-state voltage drop.

    Jan. 01, 1900
  • Vol. 51 Issue 2 246 (2021)
  • LI Tongshuai, WANG Fang, WANG Kewei, BU Jianhui, HAN Zhengsheng, and LUO Jiajun

    The thermal resistance of the 90 nm H-gate PDSOI MOSFET was investigated. The source-body diode was used as the thermometer, and the thermal resistance was obtained by measuring the relationship between the junction current and temperature, and the relationship between the junction current and MOS device power. The experimental results showed that the thermal resistance of the PMOS was larger than that of the NMOS in this technology. The reason was that the doping concentration in the body region of the PMOS was higher than that of the NMOS, and the thermal resistance increased with the increase of the doping concentration. Due to the contribution of the body-tied region to the heat conduction was decreased, the normalized thermal resistance of the H-gate device increased with the increase of the channel width. Since the thermal conductivity of SiO2 increased with temperature, the thermal resistance decreased with the increasing ambient temperature.

    Jan. 01, 1900
  • Vol. 51 Issue 2 251 (2021)
  • LIU Qicai, HE Yuan, and WANG Debo

    In order to widen the working frequency band of the piezoelectric energy harvester based on cantilever beam, a novel electrical connection scheme was proposed. By dividing the surface electrode of the cantilever beam into the symmetrical regions, the positive and negative charge under the torsional mode could be effectively collected. Then the structural size of the cantilever beam was optimized to make the resonant frequency of the bending mode and torsional mode close, so as to achieve the purpose of widening the frequency band of the piezoelectric energy harvester. Finally, according to Erturk's distributed parameter electromechanical model, the output voltage and the natural frequency of two modes were studied. It was found that when the length-to-width ratio of the cantilever beam was within the range of 3.25 to 3.35, the first-order frequency of the torsional mode was close to that of the second-order bending mode, which realized the frequency band extension of the energy harvester. This work had certain reference significance for the research and application of the piezoelectric energy harvester based on cantilever beam.

    Jan. 01, 1900
  • Vol. 51 Issue 2 255 (2021)
  • WANG Junchao, LI Haoliang, CHEN Lei, and YANG Bo

    In order to solve the problems of latch-up effect in the traditional LVTSCRs, an EEP_LVTSCR structure was proposed. By inserting a PSD/NSD active region between the drain and anode of the conventional LVTSCR NMOS, an additional recombination action was introduced. The emitter injection efficiency was reduced. The base area recombination action was enhanced through the P shallow well below NMOS, while the current gain of PNP and NPN was reduced to improve the holding voltage. Based on a 0.18 μm BCD process, the current and voltage (I-V) characteristics of the new EEP_LVTSCR and the traditional LVTSCR were simulated by TCAD simulation. Simulation results showed that the holding voltage of the new EEP_LVTSCR was increased from the traditional 1.73 V to 5.72 V. The EEP_LVTSCR was suitable for the ESD protection of 3.3 V power supply.

    Jan. 01, 1900
  • Vol. 51 Issue 2 260 (2021)
  • LI Minghao, WANG Junqiang, and LI Mengwei

    According to the urgent demands for the miniaturized packaging of micro-electromechanical systems (MEMS), a technology with high-reliability, low-cost, and high-aspect-ratio through-silicon via (TSV) structure was proposed. The core process of the technology was double-sided blind hole electroplating. The process of metal filling in the TSV structure consisted of front filling and back filling, obtaining a final TSV structure with a depth of 155 μm and a diameter of 41 μm. The electrical performance of the TSV structure was tested by power device analyzer. X-ray inspection machine and scanning electron microscope (SEM) were used to observe the defect distribution and filling conditions inside the TSV structure. The experimental results showed that the TSV samples had a good electrical conductivity and an approximate resistance value of 1.79×10-3 Ω. The hole of the sample was fully filled without voids. The research provided a promising strategy for the realization of miniaturized MEMS packaging.

    Jan. 01, 1900
  • Vol. 51 Issue 2 265 (2021)
  • LIU Yukui, CUI Wei, MAO Ruyan, SUN Shi, and YIN Wanjun

    The silicon interposer is the key module for 3D IC to achieve higher integration density. Obtaining its technical parameters is crucial to the design of the micro-system. An actually developed 2.5D silicon interposer was took as the research object. The key electrical parameters’ testing technology of Damascus copper redistribution layer (Cu-RDL) and through silicon via (TSV) were studied, and TSV parasitic capacitance was analyzed. The research results showed that the resistance of 10 μm×80 μm single hole TSV developed in 2.5D silicon interposer was 26 mΩ, and the sheet resistance of the Cu-RDL with a thickness of 1.7 μm was 9.4 mΩ/□. The measured results were consistent with that of theoretical calculations. This research work provided a basic technical support for the development and modeling of 2.5D/3D integrated process.

    Jan. 01, 1900
  • Vol. 51 Issue 2 270 (2021)
  • HAO Feifan, LI Mengwei, WANG Junqiang, and JIN Li

    According to the working principle of MEMS grating gyroscope, the gyroscope structure was simulated and manufactured at the wafer level. The structure model of the gyroscope was established in ANSYS. The analysis results showed that the driving mode and detection mode were 7 287 Hz and 7 288 Hz respectively, and the frequency difference was 1 Hz, which indicated that the structure had high sensitivity. The MEMS grating gyroscope was successfully manufactured by sputtering, wet etching, deep reactive ion etching, and anode bonding technology. The test system was built under atmospheric pressure. The measured driving mode and detection mode of the gyroscope were 7 675 Hz and 7 703 Hz respectively, and the relative error was 5.6% compared with the simulation results, which verified the feasibility of the process.

    Jan. 01, 1900
  • Vol. 51 Issue 2 276 (2021)
  • DAI Yonghong, TANG Zhengwei, LIU Xin, and LI Yuxin

    A 3D vertical structure photodetector and its manufacturing method were presented. The lower electrode of the photoelectric detector chip was welded to the substrate, and the upper electrode was connected to the amplifying circuit through the gold wire, so that the light could entere into the intrinsic layer through the side, which effectively solved the problem of heavy doping dead zone and metal electrode blocking light, reduced the light loss, reduced the composite rate, and improved the response degree. The structure of the junction in the semiconductor reduced the surface leakage current and increased the reverse breakdown voltage. The main part of the junction area was the parallel plane junction area, which effectively reduced the total junction capacitance area, reduced the parasitic time constant, and improved the response speed.

    Jan. 01, 1900
  • Vol. 51 Issue 2 281 (2021)
  • LI Shun, SONG Yu, ZHOU Hang, DAI Gang, and ZHANG Jian

    Based on the experimental data of same batch 80 samples before irradiation, and after 100, 200, 500, 1 000, 1 500 Gy total dose irradiation, the statistical law of a domestic operational amplifier LM124 under total dose irradiation was analyzed. A logarithmic normal distribution characteristics of input bias current variation was found, and the median input bias current changed within 3.6~7 nA linearly under irradiation. Also, the variation increased simultaneously with total dose. A positive linear correlation between the radiation damage and the initial value was obtained with the calculation method of the parameters. The linear coefficient (α) of the five total dose points from 100 to 1 500 Gy was 0.24, 0.31, 0.5, 0.77 and 1.07, respectively, and α showed a linear increment with the total dose. The mechanism of initial value dependence was physically explained, that is, the quality of oxide layer above EB junction determined the total dose irradiation response of the device (initial value dependence). The research results could effectively support the quantitative evaluation of radiation reliability for circuit or system based on LM124, and had a reference value for the total dose effect reinforcement screening of bipolar devices.

    Jan. 01, 1900
  • Vol. 51 Issue 2 285 (2021)
  • HUA Ning, WANG Jia, SHANG Huifeng, ZHANG Quanyuan, and GAO Xiang

    Aiming at the complexity of optimizing parameter-extraction, a new parameter-extraction method for parasitic capacitance of GaAs HEMT was proposed. When parasitic capacitance was extracted, an appropriate optimization range was set to carry out optimization reference. The three times parameter optimization was adopted to ensure the optimization accuracy and model accuracy, avoid the cycle optimization, and improve the efficiency of parameter-extraction and parameter-optimizing. This method was independent of the device structure, which reduced the error caused by the assumption of the device structure. The model parameters of 17-element small signal equivalent circuit were extracted, and the reliability of the method was verified. The results showed that the S parameter was fitting well with the measured one, and the highest fitting frequency could reach 30 GHz.

    Jan. 01, 1900
  • Vol. 51 Issue 2 290 (2021)
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