Microelectronics, Volume. 51, Issue 2, 203(2021)
Design of a Low Power and Low Delay DNU-Tolerant Latch
As the feature size of the integrated circuit devices is reduced further, the distance among the internal nodes of the latch becomes shorter and shorter. Due to the charge sharing effect among internal nodes, single event upset (SEU) affected nodes that frequently occurred in the space radiation environment have expanded from single nodes to double nodes. A new hardened latch structure which used the inherent hold property of the C-element was proposed in this paper. A complete tolerance to single node upset (SNU) and double node upset (DNU) was realized. HSPICE simulation results showed that, compared with other similar hardened designs, the power consumption of the proposed latch had decreased by 34.86% on average, the delay had decreased by 59% on average, and the power delay product had decreased by 67.91% on average. PVT analysis showed that the proposed latch structure was not sensitive to the changes in voltage, temperature and manufacturing processes.
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GUO Xinzhen, YANG Xiao, GUO Yang. Design of a Low Power and Low Delay DNU-Tolerant Latch[J]. Microelectronics, 2021, 51(2): 203
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Received: Jun. 20, 2020
Accepted: --
Published Online: Mar. 11, 2022
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