Based on a 65 nm CMOS process, a subthreshold MOSFET voltage reference with second-order temperature compensation was designed. The reference generator utilized gate-source voltage difference for CTAT voltage between two NMOS transistors, which both operated in subthreshold region to achieve second-order temperature characteristics. The second-order temperature characteristics of CTAT voltage was opposite to the second-order temperature characteristics of PTAT voltage. By using current mirror technology, the gate-source voltage difference that was complementary to absolute temperature was added to the output of the voltage reference. Simulation results showed that a temperature coefficient of 5.9 ×10-6/℃ at 1.2 V was achieved from -55 ℃ to 160 ℃. The reference generator operated under supply voltage ranging from 1.1 V to 1.5 V with an output voltage of 273.5 mV and a power consumption of 10 μW.

A programmable capacitance-voltage converter circuit for detecting small capacitance signal was presented. This circuit was composed of balance capacitor arrays, capacitance transimpedance amplifiers, sample/hold circuits, low pass filters and buffers. The capacitance detection method of modulation and demodulation was used to realize capacitance-voltage conversion. The simulation results showed that the capacitance resolution was 1.70 aF/Hz, the output voltage signal was proportional to the capacitance difference, and the determination coefficient R2 was 0.999 99. The integral capacitance value, amplification gain, balance capacitance and bandwidth of the circuit could be set flexibly by programming. The capacitance-voltage converter could be used for MEMS and other capacitive sensors.

A short-circuit protection circuit applied in intelligent high side power switch was presented. It included output short-circuit detecting circuit, delay signal generating circuit and gate-source voltage limiting circuit. NMOS transistors were used as the power transistors, so the circuit was still in the safe operating area when the circuit was short, and the reliability of high side power switch were improved. The short-circuit protection circuit was simulated in 0.6 μm HV SOI process. The simulation results showed that the power transistors were keeping in the safe operating area under the condition of hard switch fault and load short-circuit.

A single-inductor bipolar-output (SIBO) DC-DC converter was designed for the application of neural stimulation was proposed, featuring with high light-load efficiency and low design complexity. The proposed SIBO system generated both positive and negative voltages in the same time by using only one inductor and two-phase control rhythm, which greatly reduced the complexity of the control logic, and improved the efficiency. Constant on-time (COT) control was applied to improve light-load efficiency. The proposed SIBO system was powered by a single-cell lithium battery with an input voltage range of 3 V to 4.2 V. The output voltage of ±16 V, ±12 V, ±8 V, or ±4 V were enabled in different modes. Output voltage ripples of 4.5 mV of VOP and 3.4 mV of VON were achieved with a ±16 V output voltage and a 1 mA load current according to post simulation. A maximum power efficiency of 94.8% was achieved with a 1.3 mA load current. The circuit featured high efficiency, small output voltage ripple and low design complexity.

An AOT-control buck converter with Single Cycle Output Voltage Prediction (SCOVP) technique was proposed. Quasi-constant frequency operation with the input/output voltage and load variation was achieved. Furthermore, the switching frequency was set by off-chip resistor with improved accuracy. The switching frequency variation of the traditional AOT-controlled buck converter was analyzed, and an One-Shot Timer(OST) circuit with SCOVP technique was adopted. By predicting the output voltage through single duty cycle and load current, the operational frequency was stabilized. The converter was designed with in a 0.18 μm BCD process. Simulation results showed that only 13 kHz variation was realized with load current from 1 A to 5 A when the switching frequency was set as 2 MHz. Meanwhile, the switching frequency accuracy was enhanced from 88% to 99.35% with proposed SCOVP technique.

GaN half-bridge output voltage is negative during deadtime, and it brings a challenge to the signal communication of gate drive circuit of GaN power device. A novel level shifter with false eliminating circuit and zero quiescent current was designed through studying the mutual effects between the state of the level shift latch circuit, half bridge output voltage jumping and its negative pressure in deadtime. The circuit was designed in a 100 V BCD 0.18 μm process, and the layout was post-simulated in a GaN half-bridge converter with input voltage of 100 V and switching frequency of 5 MHz. The simulation showed that the delay was 4.5 ns and 1.5 ns when the half-bridge output voltage was -3 V and 100 V, respectively.

A high precision constant current LED driver based on buck topology was presented. Based on the hysteresis control mode, a new type of adaptive off-time control loop was adopted in this circuit instead of valley detection feedback loop, which indirectly achieved accurate control of the inductor valley current. Therefore, the error caused by direct sampling of the valley current was avoided, and the constant current accuracy of the system was improved. The low-side sampling was adopted to this loop to reduce the loss on the sampling resistor which improved the conversion efficiency of the system. The LED driving circuit had been designed and simulated in TSMC 0.18 μm 70 V BCD process. The simulation results showed that the maximum constant current error was not more than 0.8% within the range of 20~125 mA load current. The average current change rate was less than 1% within the range of 20~100 V output voltage.

The small-signal dynamic characteristics of the current sharing loop and the limit-cycle oscillation condition of the digital multi-phase DC-DC converter were analyzed. A digital current sharing technology based on average current was proposed, and a multi-phase DC-DC digital controller was designed. A current sharing control circuit and a digital pulse width modulator (DPWM) based on the synchronous design were presented to achieve current balancing and interleave operation. The multi-phase DC-DC digital controller chip was designed in a 0.18μm CMOS process. The simulation results showed that under 10 A~20 A load transient, the overshoot/undershoot voltage was within 20 mV, the switching frequency was adjustable from 0.5 MHz to 2 MHz, and the current sharing error was reduced from 20.8% to less than 5%.

A fast compensation driving method of the second order load with small damping coefficient was presented. According to the transfer function of the second order system, the driving signal of the second order load with small damping coefficient was transformed, and the positive and negative step response with the same damping oscillation period were added with different time to compensate the damping oscillation amplitude of a single step response, so as to achieve the fast and stable driving response of the second order load with small damping coefficient. Applied in this compensation driving method, an open loop controlled voice coil motor driver chip was designed and tape-out in a 0.18 μm CMOS technology. The results showed that the displacement amplitude of voice coil motor corresponding to the optimal driving current was only 0.925%, and the establishment time was only 7.8 ms under the condition of the resonant period of 10 ms.

The traditional multivalued reference voltage output buffers with different structures were compared and analyzed, and a novel one with low power consumption and easy compensation was proposed. The PMOS output structure and the low output impedance structure were used in the novel circuit to obtain both the higher output voltage swing and the faster transient response speed. The proposed circuit was simulated and verified in a 0.15 μm standard CMOS process with the Hspice. The simulation results showed that when the power supply voltage was 5 V and the temperature was 25℃, the output voltage upper limit could reach 4.82 V. When the value of the compensation capacitor was 3 pF, the phase margin was 86°. Under the conditions of 1.2 V input voltage, 4.5 V output voltage and 100 nA output current disturbance variation, the transient response time was 4 μs. The quiescent current was only 7 μA.

A high-order active N-path bandpass filter with harmonic rejection was designed using a three-stage second-order N-path filter unit. By inserting a negative resistance and a gyrator between the second and third stages, the Q factor, bandwidth and linearity of the filter were improved. Two clock signal with Ts/6 phase offset were used to control the second-order N-path filter unit in the final stage, which could effectively reject the third-order harmonics. The filter was designed in a 0.18-μm CMOS process. Simulation results showed that the maximum gain of the filter was 20.12 dB, the center frequency could be adjusted between 0.1 to 1 GHz, the out-of-band rejection was up to 50.2 dB@700 MHz, the third harmonic rejection was greater than 40 dB, the noise figure was in the rage of 4.71 dB to 6.9 dB, and the out-of-band input third-order intermodulation point (IIP3) was 16.3 dBm@50 MHz.

With a significant increase in chip’s integration, congestion in the placement stage of physical design had become growingly severe. Therefore, an overflow-based local congestion elimination technique was designed. Firstly, the congestion region with the highest congestion density was selected according to the overflow value. Then keepout margins of appropriate size were set for the high-pin cells in that region on the basis of simulated annealing algorithm to alleviate local congestion. The method was applied to a 40 000-gate design of the SMIC 180 nm process, and a 7 000-gate design of the SMIC 55 nm process. Compared with the optimization results of Synopsys’s ICC software, the proposed method could reduce design rule violations by 48%, shorts by 52% and total wire length by 5%. It also achieved better routing quality than existing literatures.

A parallel DC-DC converter without current sharing outer loop was designed. The average current mode was adopted to control the maximum programmed inductor current to achieve accurate current sharing of the parallel converter. The small signal model was used to analyze the current-sharing error and stability of the parallel converter. The circuit had stable current characteristics and fast transient response. An excellent load current regulation ability were achieved. The simulation results showed that the current sharing error was below 8 ‰. The current-sharing balance could be restored in 1.5 ms when the parallel converter had a load jump between heavy and light load, and could be re-established in 0.7 ms if a new converter was inserted.

This paper presented a current reference in wide voltage and temperature range based on BCD technology. Based on the feature that the TC of the on-chip poly-silicon resistor was process-insensitive, the on-chip resistor was set as the reference current defining element. First, the temperature characteristic of the on-chip resistor was analyzed, and a reference voltage whose TC was equal to the resistor’s was designed and applied on the resistor. Then, a reference current with a very low TC could be achieved. The leakage phenomenon of the parasitic element of the triode under high temperature was analyzed, and the stability of the reference current under high temperature was improved by adding a compensation transistor. This CS was based on 0.35 μm BCD process. Simulation results showed that the output current was 250 μA and the TC was 9.3×10-6/℃ within 6.5~36 V supply voltage and -55 ℃~125 ℃. The amount of current change caused by the power supply was less than 62 nA.

In order to overcome the problems of high latency, high computational complexity and high hardware structure complexity of successive cancellation (SC) decoding algorithm in 5G mobile communication systems, the freezing bit design pattern was proposed based on frozen bit, frozen bit pair and frozen interval. The design pattern included the analysis method of decoding latency and calculation complexity. The SC decoding tree was further simplified by preferentially pruning frozen bit nodes, thereby speeding up the search decoding tree. An improved pipelined tree SC decoder with N = 1 024 was implemented based on the FPGA platform. Experimental results showed that the decoding latency was 2.35 μs and the data throughput was 435 Mbit/s. Compared with the existing decoder, the decoding latency and data throughput of the decoder were optimized by 9.6% and 10.4%, respectively.

A 12.5 Gbit/s high speed SerDes transmitter based on differential encoding technology was researched and designed. This circuit was mainly composed of a parallel-serial conversion module, a de-emphasis control module and a drive module. The driving module adopted a current mode logic XOR gate structure, and the addition of dynamic load could reduce the power consumption and achieve impedance matching with the transmission line. In order to ensure the original code output, a solution for adding a differential encoding circuit to the parallel-serial conversion module was proposed for the first time, so that the process of differential encoding and decoding with the data could be completed in the transmitter. The post simulation results showed that the data transmission speed of the transmitter reached 12.5 Gbit/s. Meanwhile, the overall power consumption of the transmitter was 39 mW, and the total output jitter was 0.05 UI, which was far less than the 0.3 UI required by the JESD204B standard.

Quantum chip is the basis of constructing practical computer based on the basic principle of quantum mechanics. Through the excellent research work in recent years, research teams of various countries had developed the Si based qubit chip technology into one of the core directions of quantum computing. In this paper, the main types of Si spin qubits were summarized, and the key technologies of high fidelity, long-range coupling and other indexes required for reliable quantum computing were analyzed. Research of these technologies showed that Si was a feasible platform for the development of comprehensive quantum computing.

Drift step recovery diodes (DSRD) are generally used in ultra-wideband pulse signal sources, which can reverse nanosecond-level high-voltage pulse to the load. However, DSRD have high requirements for the rising front edge of the output pulse. A novel wide band gap material step recovery diode with variable doping in the base region was proposed in this paper, in which the doping of the traditional base region would be changed into a stepwise concentration distribution. Built-in electric field was formed by concentration gradient in base region, which would adjust the carrier distribution during the reverse pumping phase of the DSRD discharge circuit and accelerate the carrier extraction. The joint simulation of the device-circuit was performed by Sentaurus TCAD. The results showed that the maximum structure hole velocity at the end of forward injection was increased by 29% compared with the traditional structure, and the voltage rise rate was 19.7 kV/ns, which was 25% higher than the traditional structure (15.8 kV/ns). The proposed structure reduced the time of the reverse pumping stage, and the voltage rise rate of the rising front edge of the output voltage pulse was larger, while the time was shorter. As for the process, only the gas dose of the epitaxial process needed to be changed, which could be realized.

A new gate type silicon on insulator (SOI) device with a laminated embedded oxygen layer was proposed. In the anti-total ionization dose (TID) reinforcement scheme for SOI devices, the buried oxygen scheme for buried oxide (BOX), and the special S-gate scheme for STI layer were adopted. Based on Sentaurus TCAD software and Insulator Fixed Charge model, the fixed charge density was set. Base on a 0.18 μm CMOS process, the TID effect simulation of the PD SOI NMOS was proposed, and three kinds of PD SOI NMOS simulation models of strip-gate, H-gate and S-gate was established. By comparing the transfer characteristic curves, the threshold voltage drift and the transconductance degradation before and after irradiation of three devices, the anti-TID irradiation performance of the device were verified. The simulation results showed that the device with S-gate could resist kink effect, and anti-TID radiation dose of the PD SOI NMOS devices could reach 5 kGy.

In order to effectively solve the problems of large size, high signal loss and poor switching efficiency of microwave test instruments such as signal or spectrum analyzer, RF MEMS switches were applied to optimize the structure of MEMS interdigital switchable filter. The interdigital resonators with different center frequencies were selected through MEMS four-throw switches to realize the switching of four frequencies in the range of 6 to 14 GHz. The insertion loss of the four switchable frequencies obtained by optimizing calculation which used to calculate the geomemtric parameters of the filtering structure through HFSS were 1.26 dB @6.86 GHz, 1.03 dB @9.16 GHz, 1.23 dB @11.78 GHz and 1.07 dB @12.26 GHz respectively. The overall area was about 7.95 mm3. Compared with other switchable filters, this filter integrated MEMS four-throw switches with interdigital resonators, and had the advantages of low insertion loss, small size, and high integration.

The structure of NMOS device was improved by optimizing ESD implanted process parameters .The submicron ggNMOS ESD protection circuit unit was tested by transmission line pulse TLP method. The test results showed that the uniformity of electrostatic discharge current was improved after the optimization. The study of the output characteristics of the ESD-implanted NMOS showed that the drain terminal current IDT was a compound current, and it exhibited IDT-VGS differential negative resistance phenomenon under high electric field when gate-source voltage VGS was more than the threshold value VGS0. The theoretical analysis of IDT-VGS differential negative resistance phenomenon from impact ionization and snapback effect at MOS-Bipolar hybrid mode were presented. The research results of this paper could be used to optimize ESD design of CMOS/BiCMOS IC.

A novel buried buffer doped layer (IBBD) high voltage SBD was presented, and its operating characteristics were analyzed theoretically and verified by simulation. Compared with the conventional high-voltage SBD, the IBBD-SBD introduced a buried buffer doping layer above the substrate to transfer the reverse breakdown point from the PN junction protection ring area of the conventional structure to the Schottky barrier area, which improved the reverse electrostatic discharge (ESD) ability and anti-reverse surge ability, and improved the reliability of the device. Compared with the existing surface buffer doped layer (ISBD) high-voltage SBD, IBBD-SBD reoptimized the longitudinal electric field distribution in the drift zone, and further reduced the reverse leakage current and the forward guide pass pressure drop while keeping the reverse breakdown point occurring in the Schottky barrier area, thus reduced the device power consumption. Simulation results showed that the breakdown voltage of the new device was 118 V. When the reverse bias voltage was 60 V, compared with ISBD-SBD, the leakage current of the IBBD-SBD was reduced by 52.2%, and the forward voltage drop was lower.

The 60Co γ total dose radiation experiments were carried out on deep submicron NMOS and PMOS transistors. The experimental results showed that PMOS transistors had better anti-irradiation capability than NMOS transistors in terms of transfer characteristics, noise and matching characteristics. The radiation damage mechanism of NMOS transistors and PMOS transistors were analyzed theoretically. The results showed that different substrate types lead to different radiation effects of PMOS transistors and NMOS transistors. Based on the experimental and analytical results, some anti-radiation design schemes for deep submicron IC simulation were proposed.