In order to solve the problems of latch-up effect in the traditional LVTSCRs, an EEP_LVTSCR structure was proposed. By inserting a PSD/NSD active region between the drain and anode of the conventional LVTSCR NMOS, an additional recombination action was introduced. The emitter injection efficiency was reduced. The base area recombination action was enhanced through the P shallow well below NMOS, while the current gain of PNP and NPN was reduced to improve the holding voltage. Based on a 0.18 μm BCD process, the current and voltage (I-V) characteristics of the new EEP_LVTSCR and the traditional LVTSCR were simulated by TCAD simulation. Simulation results showed that the holding voltage of the new EEP_LVTSCR was increased from the traditional 1.73 V to 5.72 V. The EEP_LVTSCR was suitable for the ESD protection of 3.3 V power supply.