A high speed sample and hold (S/H) circuit using low threshold technology was presented. Capacitor flip-around architecture was used for S/H circuit. Gate-bootstrapped switch technique was used to improve linearity. Bottom-plate sampling technique was adopted to reduce charge injection effect. The proposed amplifier and the traditional telescopic common-source common-gate amplifier had the same circuit structure. What’s the difference was that the proposed amplifier used a low threshold technology with the advantages of high gain and bandwidth by adopting low threshold device compensation based on a specific process, and it improved the sampling rate of the sample-and-hold circuit. The circuit was designed and fabricated in a 0.18 μm CMOS technology, and the sampling clock frequency was more than 125 MHz. The simulation results showed that SINAD was 90.91 dB, SFDR was 91.45 dBc, and the chip area was 0.8 mm×0.5 mm.