The silicon interposer is the key module for 3D IC to achieve higher integration density. Obtaining its technical parameters is crucial to the design of the micro-system. An actually developed 2.5D silicon interposer was took as the research object. The key electrical parameters’ testing technology of Damascus copper redistribution layer (Cu-RDL) and through silicon via (TSV) were studied, and TSV parasitic capacitance was analyzed. The research results showed that the resistance of 10 μm×80 μm single hole TSV developed in 2.5D silicon interposer was 26 mΩ, and the sheet resistance of the Cu-RDL with a thickness of 1.7 μm was 9.4 mΩ/□. The measured results were consistent with that of theoretical calculations. This research work provided a basic technical support for the development and modeling of 2.5D/3D integrated process.