A novel energy-efficient capacitor switching scheme for high speed successive approximation register (SAR) analog-to-digital converters (ADC) was proposed. Based on the 2bit/cycle architecture, two differential split capacitor arrays were employed as the digital-to-analog converter (DAC). The proposed scheme decreased the dynamic energy consumption of the capacitor arrays and the total capacitor area while it speeded up the settling of the capacitor by one-side charging operation. During the last quantization cycle, the common-voltage was introduced only to one side of the differential arrays, and just one comparator was enabled. By these, the proposed scheme got more resolution and further decreased the dynamic energy consumption. The proposed scheme achieved an 83% reduction of the average switching energy and a 50% reduction of the total capacitor area while it almost doubled the conversion speed compared with the conventional 1bit/cycle scheme, and it got different degrees of improvement in resolution, total capacitor area and energy consumption when compared with other 2bit/cycle schemes.