A 12 bit successive approximation register (SAR) analog to digital converter (ADC) for biomedical signals was designed in a 0.18 μm CMOS process. A segmented capacitor array with one redundant bit was adopted in the digital to analog converter (DAC). The comparator used a dynamic comparator composed of complementary input pairs to reduce its noise and power consumption. The gate voltage bootstrap switch with stack transistors and virtual transistors was used in the sample-and-hold circuit. Besides, aiming at the sparsity of biomedical signals, the difference between the two sampling voltages was detected by delaying the reset time of the upper plate. Then the sampling rate could be switched adaptively. Under the condition of 120 kS/s sampling rate and 1 V supply voltage, the simulation results showed that the SAR ADC consumed only 4.65 μW, the spurious-free dynamic range (SFDR) was 76.29 dB, the figure of merit (FOM) was 16.9 fJ/(conv·step), and the effective number of bit (ENOB) reached 11.16 bit.

A dual-mode 28 GHz power amplifier (PA) for 5G applications was designed in a domestic 40 nm CMOS process. The large-sized transistors were used in the power stage to obtain higher saturated output power. The common-mode oscillation problem of power amplifier caused by large size transistors was eliminated by using non-center tapped transformer. A large resistor was utilized at the gate of the common-gate transistor in the cascode topology to improve high frequency stability. The common gate shorting technique was applied to solve the differential gain loss produced by this large resistor. A varactor was used in the inter-stage matching network to realize a dual-mode switching, so high power gain and wide bandwidth were obtained respectively. The post-circuit simulation results showed that, in high gain mode, the dual-mode PA achieved a saturated output power of 20.8 dB, a power added efficiency of 24.5% and a power gain of 28.1 dB. In high bandwidth mode, a saturated output power of 20.6 dBm, a power added efficiency of 22.6% and a 3 dB bandwidth of 12.2 GHz were obtained.

A high precision reference circuit was designed in a 0.35 μm CMOS process. All MOSFETs were adopted to avoid resistors, leading to smaller chip area. A new variable resistance method was adopted to realize accurate compensation. A two-stage voltage reference source was adopted to improve the power suppression ratio. The voltage reference source was simulated using Cadence Virtuoso. The results showed that when the temperature ranged from -40 ℃ to 125 ℃, the reference voltage was 1.146 V and the temperature coefficient was 1.025×10-5℃-1. At 27 ℃, the static current was 6.57 μA, and the PSRR was -96.64 dB @100 Hz and -93.94 dB @10 kHz. The linear adjustment degree of the voltage reference was 0.047% at 2.9 to 5 V power supply voltage. This circuit was suitable for analog integrated circuits with low power consumption and high precision.

A desaturation and over-current detection circuit with soft turn-off and under-voltage protection for IGBT was designed in a 0.4 μm standard BCD process. The circuit was designed and built by the Cadence software, and the Hspice software was used to run the simulation and debugging. The results showed that the UVLO output a low level to force the device to be in the off state at the beginning. When the UVLO output a high level, the DESAT was activated and began to detect the collector voltage. Once the collector voltage exceeded the preset threshold voltage of 6.5 V, a soft turn-off action was performed in the device. The soft turn-off duration time was 10 μs. The detection circuit realized the cooperative protection of IGBT by the UVLO and DESAT.

Based on a 0.18 μm BCD process, an externally adjustable foldback current-limit circuit for LDO was proposed. This new circuit had both current limiting and foldback functions. The current limiting part clamped the maximum output through a loop formed by current mirrors. The foldback part used a negative feedback loop formed by an error amplifier to generate a current foldback output current proportional to the output voltage. Compared with traditional current-limit structures, this new structure saved a lot of power consumption and protected the power MOSFET from being burnt. Compared with the traditional foldback structures, this structure could easily adjust the current limit and the foldback point by adjusting two external resistors to avoid the voltage regulator from latching up. At 1.2 V typical output, the simulation verification results of the LDO circuit showed that the current limit range was 215~350 mA, and the foldback voltage range was 450~900 mV while adjusting four different external resistance values. The power consumption during short-circuited region was reduced to 230 mW.

To process the laser pulse echo signal with wide dynamic range, an analog front end with adaptive gain control technology was designed. By step adjustment for the transimpedance gain of the transimpedance amplifier, the input current and the output voltage were approximately linear in the range of 1 μA~1 mA. The proposed self-trigged and enabled method could continuously receive echo signals without external clearing signal. A novel differential shift time discrimination circuit was proposed, which could effectively reduce the walking error. The circuit was designed in a 0.11 μm CMOS process. The post-simulation results showed that the -3 dB bandwidth of the circuit was 530 MHz, the maximum transimpedance gain was 103 dBΩ, the equivalent input noise current spectral density was 6.47 pA·Hz-1/2@350 MHz, the input dynamic range was 60 dB, and the power consumption was less than 100 mW. The analog front end circuit design was suitable for time-of-flight pulse LIDAR.

A low phase noise and wideband frequency synthesizer was designed and implemented in a 0.18 μm SiGe BiCMOS process. The approaches and methods for optimizing the phase noise and widening the frequency band was analyzed for frequency synthesizer based on PLL type. A low output phase noise reference buffer and a high speed delta-sigma modulator were proposed., A conventional charge pump was improved to reduce ouput noise. A frequency divider based on ÷2/3 was used to implement a wideband working frequency. The measurement results showed that the phase noise floor of frequency synthesizer was -232.2 dBc/Hz, and the working frequency could cover 1~20 GHz.

Based on the SMIC 0.18 μm CMOS process, a reconfigurable second-order Σ-Δ modulator was designed for the applications of adaptive systems. With the introduction of dynamic voltage scaling technique, how to reduce the power supply voltage to save ADC power consumption under different input signals had been studied. First, the effects of non-ideal parameters on system performance had been analyzed by mathematical modeling under Simulink, and then the circuit design had been conducted under Cadence, with the layout design and post-simulation completed. In addition to conventional adjustment schemed such as the op amp’s input differential pair width-to-length ratio and tail current, the power supply voltage could be adjusted according to the input signal amplitude to further improve the system flexibility. The simulation results showed that if the ENOB required by the system was 12 bit, the modulator’s power consumption was reduced from 123 μW to 51 μW when the power supply voltage was decreased from 3.3 V to 1.8 V, indicating a significant power saving effect. The area of the designed modulator’s layout was 0.06 mm2.

A novel PWM comparator with dynamic reference was proposed with the benefits of high sensitivity and ultra-low power consumption. The proposed dynamic comparator adopted the dynamic reference and multi-path positive feedbacks. In the comparator, the continuous input signal was used to be compared with the dynamic reference to obtain a series of discrete digital signals. By the afterward logical processing, the obtained digital signals were converted into the PWM signals with the changed duty cycles. Based on a 65 nm CMOS process, this circuit was verified at a 1.2 V supply voltage and a 200 MHz clock frequency. The results showed that the overall delay time was increased. The average current was 5.958 μA, and the resolution was 800 μV. The power consumption was only 8.1 μW, which was 5.2% of the traditional static PWM comparator.

A 25 Gbit/s adaptive decision feedback equalizer (DFE) with one infinite impulse response (IIR) tap was designed in a 65 nm CMOS technology. In this DFE, a half rate speculative structure consisting of one stacked selector and two latches was adopted to reduce the feedback delay on the critical path. An adaptive engine based on the improved least mean square (LMS) algorithm was employed to improve the convergence of the tap coefficient. An improved fT doubler was used as the output buffer for higher bandwidth and pre-emphasis. The simulation results showed that the DFE could adaptively compensate up to 20 dB channel attenuation at 25 Gbit/s signal rate while its output jitter was less than 10 ps. The average power consumption of the whole circuit was about 120.5 mW at differential process corners from a voltage supply of 1.2 V.

The principle and implementation of Σ-Δ ADC’s down sampling filter and up sampling filter in the hearing aid chip was presented. Through optimizing the structure and multiplexing the filter’s coefficient, the chip area was reduced. The filter coefficients were programmable to realize the dynamic switching between passband flatness and transition bandwidth as well as the different sampling rate. The circuit was fabricated and verified by MPW in SMIC 130 nm 1P8M CMOS process. The results showed that the filter supported 16 kHz and 32 kHz sampling rates, which could meet the needs of DSP for hearing aid with different sampling rates. The passband ripple of the cascaded filter was 0.001 dB, the stopband attenuation was 80 dB, and the maximum group delay was 3.877 ms. It could meet the requirement of signal conversion circuit of hearing aid.