A charge pump phase-locked loop with a locking frequency range of 16~24 GHz was designed in a 018 μm CMOS process. A high performance frequency discriminator, a charge pump and a third-order Σ-Δ modulator were adopted to reduce the reference spurs on output clocks. By introducing LFSR into the Σ-Δ modulator, a pseudo-random sequence was generated and the fractional spurs was further reduced. The simulation results showed that the current mismatch ratio was only 01% and the fractional spur was -50 dBc @1 MHz at 03~15 V output voltage.