A four-channel 8-bit 216 GS/s time-interleaved successive approximation register analog-to-digital converter (TI-SAR ADC) was designed. A dual-loop structure with an asynchronous clock loop and a data loop was explored to achieve high speed operation. A dynamic comparator with reset switches was employed to shorten the quantization time and improve the comparison accuracy. A reversed monotonic switching sequence approach was utilized to increase the input common-mode voltage and improve the quantization speed. The chip was designed in a 55 nm CMOS technology. The post-layout simulation results showed that the TI-SAR ADC achieved an FOM of 212 fJ/(conv.step), an SNDR of 427 dB and an SFDR of 53 dB under Nyquist input frequency, while consuming 426 mA current from 12 V power supply. The ADC occupied an area of 34 mm2.