A novel PWM comparator with dynamic reference was proposed with the benefits of high sensitivity and ultra-low power consumption. The proposed dynamic comparator adopted the dynamic reference and multi-path positive feedbacks. In the comparator, the continuous input signal was used to be compared with the dynamic reference to obtain a series of discrete digital signals. By the afterward logical processing, the obtained digital signals were converted into the PWM signals with the changed duty cycles. Based on a 65 nm CMOS process, this circuit was verified at a 1.2 V supply voltage and a 200 MHz clock frequency. The results showed that the overall delay time was increased. The average current was 5.958 μA, and the resolution was 800 μV. The power consumption was only 8.1 μW, which was 5.2% of the traditional static PWM comparator.