A 25 Gbit/s adaptive decision feedback equalizer (DFE) with one infinite impulse response (IIR) tap was designed in a 65 nm CMOS technology. In this DFE, a half rate speculative structure consisting of one stacked selector and two latches was adopted to reduce the feedback delay on the critical path. An adaptive engine based on the improved least mean square (LMS) algorithm was employed to improve the convergence of the tap coefficient. An improved fT doubler was used as the output buffer for higher bandwidth and pre-emphasis. The simulation results showed that the DFE could adaptively compensate up to 20 dB channel attenuation at 25 Gbit/s signal rate while its output jitter was less than 10 ps. The average power consumption of the whole circuit was about 120.5 mW at differential process corners from a voltage supply of 1.2 V.