Conventional passive noise shaping SAR ADCs have poor noise-shaping ability because of the gain and phase error of passive switching capacitor integrator. On the basis of passive noise shaping, an active and passive noise shaping SAR ADC was designed in this paper, which integrated low gain OTA and positive feedback circuit, and only a small amount of power consumption was increased, while the gain and phase errors of passive noise shaping module were nearly eliminated. The results showed that the bandwidth of the noise-shaped 10-bit SAR ADC was 10 kHz, the sampling rate was 320 kHz, the power consumption was only 109 μW, and the effective number of bit (ENOB) was 156 bit. The ENOB were more than 15 bit at -40 ℃~85 ℃ and different process corners.

An ultra-wideband sampling/holding circuit was designed in a 013 μm SiGe BJT process. The auxiliary switching circuit was used to process the signal in advance, which improved the linearity of the circuit. The fully differential open loop structure and multi-stage cascade output buffer were adopted to reduce the sagging rate effectively. The simulation was performed by Cadence Spectre at 5 V supply voltage and 100 fF load capacitance. The results showed that the clock frequency was 4 GHz under coherent sampling. At high frequency of 18 GHz, the SFDR reached 6399 dB, so the high frequency characteristics was good. The bandwidth of the circuit was up to 251 GHz. It was suitable for high speed A/D converters.

The needs of modern wideband digital receivers for high performance analog-to-digital converters (ADCs) are increasing gradually, but the electronic ADCs cannot realize UWB direct digital sampling due to carrier migration rate limit. Based on the characteristics of ultra-wideband and ultra-high speed of photonic technology, an ADC technology with optoelectronic hybrid structure was proposed in this paper. Optical sampling based on ultrashort optical pulse was used to replace the sample/hold (S/H) circuit used in electronic semiconductor technology to greatly improve the sampling bandwidth, and time division multiplexing and multichannel ADC quantization technology were used to realize digital coding. Finally, the system performance was improved by digital domain equalization and linearization. The direct sampling of microwave signals with frequency greater than 24 GHz, and the sampling signal-to-noise ratio greater than 40 dB were realized, which provided an effective way for UWB microwave signals to be directly digitized with high precision.

A high gain cascode low noise amplifier (LNA) for 5G communication band of 22~4 GHz was designed and implemented in a 025 μm GaAs pHEMT process. By combining the parallel RC feedback with the common gate grounding capacitor, the LNA with broadband and high gain was completed without the use of source inductance. The measurement results showed that the gain of 22~4 GHz band was better than 24 dB, the output third-order intermodulation (OIP3) was 28 dBm, the noise figure (NF) was less than 078 dB, the power consumption was 190 mW, and the chip area was (810×710) μm2. The Figure of Merit (FOM) was 144 dB, which had certain advantages compared with relevant LNAs.

A thin film bulk acoustic wave resonator (FBAR)-based differential Colpitts oscillator was presented. Compared to the traditional architectures, the proposed Colpitts oscillator removed the tail current source to reduce the phase noise. The combination of the cross-coupled pair and transformer in the oscillator increased the effective gm, reduced the star-up current requirement, increased output swing under a lower supply voltage, and reduced the phase noise. The oscillator operated in a Class-C state by adjusting the bias voltage. The current utilization was effectively improved to reduce the phase and the power consumption. The 1865 GHz-FBAR with high Q value was used as resonant network of the oscillator, and the CMOS circuit was completed in the SMIC 55 nm RFCMOS process. Simulation results showed that the output carrier frequency was 1876 GHz under 06 V voltage supply. This oscillator achieved a phase noise of -84 dBc/Hz, -146 dBc/Hz at 1 kHz, 1 MHz offset frequency respectively. The power dissipation was only 83 μW, and the FOM value was -225 dB.

In order to achieve high conversion efficiency in a wide load range, a hybrid modulation mode of DC-DC converter was designed, which combined PWM modulation with PSM modulation. A simple self-adaptive modulation switching circuit was designed, and a new synchronous generator circuit of minimum duty cycle signal OSC, VRAMP signal and clock signal VCLK was designed using slope descent edge of ramp generator circuit to simplify the circuit scale. Under light load, the modulation mode was automatically switched into PSM modulation mode by detecting duty ratio and output voltage simultaneously, which reduced the operating frequency of the switching circuit, and the static loss was reduced by 40%. The circuit was designed in a 65 nm CMOS process. The simulation results showed that the circuit could switch smoothly between the two modulation modes, and the working efficiency was improved to 863% at 1 mA load.

A buck-boost negative shutdown voltage generation circuit was designed. By introducing a dynamically adjustable off-time timing module, a segmented current-limit module and a ripple based high speed detection module, a stable negative gate voltage supply was achieved during the fast switching of depleted GaN devices, which effectively eliminated the occurrence of Miller open when depletion-mode GaN devices were used in high-voltage applications. The circuit was designed and simulated in a 035 μm BCD process. The results showed that the circuit could output stably a negative voltage of -14 V in a wide input range, the operating efficiency could reach 80%~87% under 20~130 mA constant load current. The output voltage of GaN device kept stable during gate switches switching at 05~1 MHz operating frequency. This circuit met the needs of high voltage applications.

Based on the short-circuit-open-circuit-load-through(SOLT)calibration principle combined with MEMS switches, a miniaturized multifunctional electronic calibration module was designed. The simulation results showed that this electronic calibration kit required only 2 steps for dual-port calibration in the frequency band of 01~20 GHz. The insertion loss was less than 09 dB at direct circuit condition, the return loss was less than 048 dB at open circuit condition, the return loss was less than 039 dB at short circuit condition. The overall size was 25 mm×12 mm×08 mm. The MEMS electronic calibrator kit had the advantages of small size, low loss and cost, high calibration accuracy and efficiency. It was suitable for the applications of millimeter-wave measurement and miniaturized intelligent calibration.

Traditional VGA is not suitable for biomedical applications because of its low linearity. In this paper, the traditional structure based on programmable transconductance was analyzed, and the relationship between loop gain and distortion was obtained. Based on this, a new type of VGA based on programmable transconductance was designed, which improved the linearity of VGA. The simulation results showed that the current consumption of the circuit was 10 μA at 12 V supply voltage and 0~30 mV input signal amplitude range. The total harmonic distortion of VGA was less than 05%, the IM3 was reduced by 14 dB, the IIP3 was 1857 dBm, and the equivalent input noise was 616 nV in the range of 01 Hz to 100 kHz.

A linearization charge pump was designed in a 018 μm SiGe BiCMOS process, and the principle of this linearization charge pump was analyzed. By using a charging and discharging circuit based on sample-and-hold principle, and combined with a specific sequential logic circuit, the charge pump achieved the linearization and low fpfd spur of PLL. This linearization charge pump was applied to a PLL, and the measurement results of PLL showed that the phase noise @100 kHz offset frequency was improved by 9 dB compared with that of nonlinearity charge pump, and the fpfd spur was improved by 1205 dB compared with that of conventional linearization charge pump.

The basic principle of switching power supply transient load and the relationship between the output voltage drop and the control loop were analyzed. Besides, several methods to reduce the output voltage drop were discussed systematically, and the digital nonlinear control aiming at increasing the transient load was proposed. Based on above methods, the effect of loop bandwidth, rectification mode, and nonlinear control on the transient response of the switching power supply were comprehensively evaluated. Finally, a DC-DC converter with fast transient load response was designed by using this nonlinear control. The experimental results showed that the output voltage drop could be reduced by 60%, and the recovery time could be shortened by 30% under a pulse load. The experimental results met the design requirements.

According to the requirement of miniaturization, a digital optical transceiver microsystem was designed. Based on system-in-package technology, the integrated ceramic pin grid array package with tube shell and substrate was used to integrate all kinds of components such as bare chips, optical devices and resistance capacitances required by optical transceiver system. Through layout design, signal integrity, power integrity and thermal stress simulation, the sample was developed. After testing, the signal receiving SNR was greater than 65 dBFs, and SFDR was greater than 86 dBc. The module function was stable, and the specification was reliable, which met the actual needs.

A readout circuit with hybrid signal translation applied to low field nuclear magnetic resonance (NMR) was proposed. The readout circuit system was mainly composed of front-end amplifiers, receivers and back-end analog-to-digital converters. The natures of the proposed hybrid signal translation technique were the linearity enhanced through hybrid mode detection of phase domain and voltage domain, as well as the gain distribution between the amplifiers and the ADC. The circuit was designed in a 018 μm CMOS process. The simulation results showed that the power consumption of the whole circuit was 05 mW at a power supply voltage of 12 V. The input referred 1 dB compression point and IIP3 of the front-end amplifiers were -931 dBm and -598 dBm respectively. The input referred noise of the receiver was only 2 nV·Hz-1/2.

A multi-source energy harvesting chip was designed in a standard 018 μm CMOS process, which could efficiently collect piezoelectric, photoelectric, thermoelectric and RF energy simultaneously. The collecting chip consisted of a variety of energy interface circuits, a reconfigurable charge pump and an adaptive control circuit. In the reconfigurable charge pump, the charge redistribution loss was reduced by adjusting the voltage conversion rate and switching frequency, the conversion efficiency was improved, and the input voltage range was expanded. In the adaptive control circuit, the output voltage of the system was controlled by the constant on-time method, and the peak voltage generated was multiplexed to control the working state of the charge pump, which reduced the complexity and power consumption of the circuit. The simulation results showed that the overall dynamic power consumption of the chip was 33 μW, and the maximum energy conversion efficiency was 603%. The layout size was 1 672 μm×1 990 μm..

Aiming at the problem of poor insertion loss and isolation of MEMS single-pole multi-throw (SPMT) switches, a single-pole five-throw (SP5T) MEMS switch was designed to realize balanced signal distribution and low loss transmission through a snowflake power splitter. Simultaneously, the weak contact of the switch was effectively reduced, and the stability of the switch contact was enhanced by designing the H-shaped top electrode structure. The radio frequency and mechanical performance of the designed switch were analyzed and simulated by using HFSS and COMSOL software. The simulation results showed that the insertion loss of the five ports was below 02 dB @20 GHz, the isolation was above 23 dB @20 GHz, and the driving voltage was 24 V. These targets were better than the conventional SPMT switch. The SP5T MEMS switch could be used in multi-task, multi-channel tunable devices, and it had application values in communication and microwave test systems.

In order to solve the reliability problem of PD driver circuit, a high precision PD driver circuit with hysteresis structure based on the traditional circuit was designed and implemented. A symmetrical double-path structure were adopted to adjust the rising and falling edge time of the signal respectively, and the hysteretic conduction method was used in each path to improve the control precision. The current limiting mode was adopted to solve the oscillation phenomenon caused by parasitic effect and improve the reliability of communication. This driver circuit was fabricated in TSMC 018 μm CMOS process. The tested results showed that, when the external frequency of BMC square wave was 300 kHz, the rising and falling edge time of voltage signal on the cable were 340 ns, no obvious oscillation. The static power consumption of this circuit was less than 400 μA, and it had good practical value.

A compact time-to-amplitude converter (TAC) for single-photon time-of-flight (TOF) measurement was designed. An innovative current integral method based on Wilson current source was proposed to effectively reduce the circuit occupied area and to significantly enhance the time full-scale range (FSR) of the TOF measurement. Designed in a standard 018 μm CMOS technology, the filling factor (FF) of 268% was achieved through a compact TAC structure for a single-photon avalanche diode (SPAD) pixel. The post-layout simulation results further revealed that the TAC featured 230 ps timing resolution in a 120 ns FSR. Furthermore, the TAC was characterized by a low differential nonlinearity (DNL) of 005 LSB and a low integral nonlinearity (INL) of 11 LSB in the whole detectable time range. Additionally, a low nonuniformity below 05 % was obtained across 512 in-pixel TACs by Monte Carlo simulation. The proposed TAC was very suitable for high-density time-correlated single-photon counting (TCSPC) detectors.

A high efficiency approximate DCT circuit based on multiple voltages was designed. By approximating the arithmetic units and coefficients in DCT, the energy consumption of DCT was reduced by logic simplification. To further improve the energy efficiency of the approximate DCT circuit, low-voltage supplies were used in some cells of DCT, so the circuit achieved lower energy consumption while maintaining the circuit performance. Based on 018 μm CMOS technology, the results showed that the energy consumption of the proposed method was reduced by 314% and 138% compared with the same circuits at standard voltage and low voltage, respectively, while keeping same frequency as the standard design. Compared with the traditional approximate CORDIC DCT design, the circuit reduced the energy consumption by 447%, while providing 14 dB higher output accuracy than the traditional approximate CORDIC DCT circuit.

A new type of RF small-signal equivalent circuit model and an analytical modeling method based on rational function fitting were proposed for 3 nm gate-all-around device. At first, the bias-independent extrinsic gate, source and drain resistance, gate-to-source/gate-to-drain capacitance, and substrate capacitance and resistance were extracted. Then, the bias-dependent intrinsic parasitic parameters were extracted under different bias of the device. The 3D TCAD and Matlab were used to simulate the device and get parasitic parameters by fitting, and the parameter results were put in ADS for verification. The results showed that the maximum error of S parameter between TCAD simulation and equivalent circuit simulation was less than 269% at 10 MHz~300 GHz frequency range. The accuracy of the established model and modeling method were verified. The research results had a reference value for RF IC design.

Compared with traditional piezoelectric monocrystalline SAW devices, thin film SAW devices have the advantages of low cost, easy miniaturization and easy integration. The research progress of several thin film SAW devices was reviewed in this paper. Firstly, several common thin film preparation methods were summarized. Then thin film SAW devices were divided into high frequency devices and high temperature devices according to different applications. According to the two types, five typical thin film SAW devices in recent years were reviewed, and their fabrication process, basic structure and high frequency/high temperature characteristics were introduced. Finally, these five kinds of thin film SAW devices were compared, and the prospect of the future development of thin film SAW devices was proposed, which had certain guiding significance for the practical application and promotion of thin film SAW devices.

The high temperature characteristics of 28 nm ultra-thin-body fully depleted (FD) SOI MOSFET with low threshold voltage(LVT)structure were studied. The device was tested at 300 ℃, and parameters were compared between FD-SOI and partially depleted (PD) SOI. Combined with theoretical analysis, it was proved that ultra-thin-body FD-SOI had lower threshold voltage drift rate and sub-threshold slope than PD-SOI at high temperature. When operating at 300 ℃, the parameters of SOI MOSFET degrade, the threshold voltage decreased, the leakage current increased, and the gate’s ability to control the channel current was greatly reduced. The design of the ultra-thin body FD-SOI allowed for more stable high temperature performance of the device, thus the operating temperature of the circuit was increased to 300 ℃.

Based on TSV technology, a cumulative NMOS varactor diode applied to three-dimensional integrated circuits was proposed. Compared with the conventional cumulative NMOS varactor, the TSV-based cumulative NMOS varactor had the advantages of high capacitance density and high integration. The impacts of TSV height, TSV diameter, junction depth and width of source region and drain region on the performances of the proposed varactor diode were analyzed. The results showed that the capacitance density could be increased by increasing the TSV height or TSV diameter. The voltage sensitivity could be improved by reducing the junction depth of the source region and drain region. And by increasing the width of the source region and drain region, the inhibition ability of electron generation by the hole in the channel could be improved. An analytic model was added to the above comparison. Finally, the fabrication process of the varactor diode was given.

A new PMOS device trigger SCR device (PMTSCR) was proposed to reduce the trigger voltage for electrostatic discharge (ESD) protection. The turn-on of the PMTSCR device was determined by the channel length of the parasitic PMOS and the parasitic well resistances RPW and RNW of the SCR device. The device featured low trigger voltage. The experimental results showed that the trigger voltage of the PMTSCR device reduced from 63 V to 44 V, and was 30% less than that of the traditional low voltage trigger SCR device (LVTSCR), while the ESD leakage current of the device remained unchanged.

Based on Ansys software, a 3D model of multilayer Cu interconnect structure were established with three-level sub-modeling technology. The effects of elastic modulus and coefficient of thermal expansion of the dielectric material of the global interconnect lines in the 10-layers Cu interconnect structure on the thermal stress were studied. On these basis, the global interconnect lines dielectric material was optimized. The results showed that the coefficient of thermal expansion of the global interconnect lines dielectric material had less effect on the thermal stress of Cu interconnect structure, but the elastic modulus had a great influence. The thermal stress of dielectric material in each layer was proportional to the elastic modulus, while the interface thermal stress in SiN was inversely proportional to it. Finally, to reduce the thermal stress of the key positions of Cu interconnect structure, the selection of the global interconnect lines dielectric material was optimized through selecting different material combinations, then the reliability of Cu interconnect structure was improved.

A symmetrical square enclosed layout transistor (SS-ELT) NMOS device structure was introduced. Equivalent aspect ratio W/L model and total ionizing dose (TID) radiation-hard performance of the SS-ELT NMOS were also studied. Based on regional decomposition and conformal mapping, et al., the model of equivalent aspect ratio W/L was derived. The chips were fabricated in a 018 μm BCD process. Both standard NMOS and SS-ELT NMOS with different sizes were tested under irradiated environment and non-irradiated environment. The tested results showed that the percentage error of equivalent aspect ratio W/L model of the SS-ELT NMOS could be as low as 5%. Under the condition of 10 kGy TID, the off-state leakage current of the SS-ELT NMOS could still be maintained at a very low level, which reflected its great TID tolerance.

In the test of electrostatic discharge (ESD) capacity, a special digital circuit for multi-power domain failed at 1 700 V of the human body model (HBM). The failure position after electrostatic test was located by the HBM test and the optical beam induced resistance change (OBIRCH) failure analysis. According to the failure analysis results and theoretical analysis, the reason was due to weak reverse electrostatic capacity of the electrostatic diode. The transistors were used to replace the electrostatic diodes, and the interior of OUT2 port was optimized for electrostatic layout design. After the revision, the ESD protection capability of the circuit reached more than 2 500 V. The results of this study had reference value for ESD failure analysis and robustness improvement of multi-power supply domain digital circuits.