A 12 bit successive approximation register (SAR) analog to digital converter (ADC) for biomedical signals was designed in a 0.18 μm CMOS process. A segmented capacitor array with one redundant bit was adopted in the digital to analog converter (DAC). The comparator used a dynamic comparator composed of complementary input pairs to reduce its noise and power consumption. The gate voltage bootstrap switch with stack transistors and virtual transistors was used in the sample-and-hold circuit. Besides, aiming at the sparsity of biomedical signals, the difference between the two sampling voltages was detected by delaying the reset time of the upper plate. Then the sampling rate could be switched adaptively. Under the condition of 120 kS/s sampling rate and 1 V supply voltage, the simulation results showed that the SAR ADC consumed only 4.65 μW, the spurious-free dynamic range (SFDR) was 76.29 dB, the figure of merit (FOM) was 16.9 fJ/(conv·step), and the effective number of bit (ENOB) reached 11.16 bit.