With a significant increase in chip’s integration, congestion in the placement stage of physical design had become growingly severe. Therefore, an overflow-based local congestion elimination technique was designed. Firstly, the congestion region with the highest congestion density was selected according to the overflow value. Then keepout margins of appropriate size were set for the high-pin cells in that region on the basis of simulated annealing algorithm to alleviate local congestion. The method was applied to a 40 000-gate design of the SMIC 180 nm process, and a 7 000-gate design of the SMIC 55 nm process. Compared with the optimization results of Synopsys’s ICC software, the proposed method could reduce design rule violations by 48%, shorts by 52% and total wire length by 5%. It also achieved better routing quality than existing literatures.